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1. 发明申请

US20050172105A1 Coupling a general purpose processor to an application specific instruction set processor 失效
标题翻译：将通用处理器耦合到特定于应用程序的指令集处理器
公开(公告)号：US20050172105A1
公开(公告)日：2005-08-04
申请号：US11035934
申请日：2005-01-14
申请人： Andreas Doering , Silvio Dragone
发明人： Andreas Doering , Silvio Dragone
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3877 , G06F9/30079 , G06F9/3017 , G06F9/382 , G06F9/3879
摘要： Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.
摘要翻译：提供用于将通用处理器（GPP）耦合到应用特定指令集处理器（ASIP）的方法，系统和装置，使得GPP可以包括通常不包括其指令集架构（ISA）的一部分的执行指令，。 GPP通过协处理器端口耦合到ASIP，使得GPP向端口发出的指令被传送到ASIP的新型预解码器模块。预解码器模块将GPP指令转换为在ASIP中执行的ASIP指令的操作码或ASIP指令存储器中的一个地址，该地址标识用于定义复杂的专用功能的多个ASIP指令的起始地址。一旦ASIP执行了指令，它将与GPP共享执行结果。以这种方式，GPP利用ASIP更快地执行特定应用程序/程序的能力。

2. 发明申请

US20050055594A1 Method and device for synchronizing a processor and a coprocessor 审中-公开
标题翻译：用于同步处理器和协处理器的方法和装置
公开(公告)号：US20050055594A1
公开(公告)日：2005-03-10
申请号：US10924185
申请日：2004-08-23
申请人： Andreas Doering , Silvio Dragone
发明人： Andreas Doering , Silvio Dragone
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F1/12
摘要： A system and method for synchronizing a processor and a coprocessor includes a processor and coprocessor working off a thread, wherein the thread includes a thread control instruction (stopthread) for controlling the timing of this thread. When the processor executes the thread control instruction this thread is stopped with the help of the thread control instruction until a wake up signal from the coprocessor allows the continuation of working off of this thread.
摘要翻译：用于同步处理器和协处理器的系统和方法包括处理器和处理线程的协处理器，其中线程包括用于控制该线程的定时的线程控制指令（stopthread）。当处理器执行线程控制指令时，借助线程控制指令停止该线程，直到来自协处理器的唤醒信号允许继续关闭该线程。

3. 发明申请

US20080098202A1 Coupling a general purpose processor to an application specific instruction set processor 失效
标题翻译：将通用处理器耦合到特定于应用程序的指令集处理器
公开(公告)号：US20080098202A1
公开(公告)日：2008-04-24
申请号：US11926090
申请日：2007-10-28
申请人： Andreas Doering , Silvio Dragone
发明人： Andreas Doering , Silvio Dragone
IPC分类号： G06F9/06
CPC分类号： G06F9/3877 , G06F9/30079 , G06F9/3017 , G06F9/382 , G06F9/3879
摘要： Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.
摘要翻译：提供用于将通用处理器（GPP）耦合到应用特定指令集处理器（ASIP）的方法，系统和装置，使得GPP可以包括通常不包括其指令集架构（ISA）的一部分的执行指令，。 GPP通过协处理器端口耦合到ASIP，使得GPP向端口发出的指令被传送到ASIP的新型预解码器模块。预解码器模块将GPP指令转换为在ASIP中执行的ASIP指令的操作码或ASIP指令存储器中的一个地址，该地址标识用于定义复杂的专用功能的多个ASIP指令的起始地址。一旦ASIP执行了指令，它将与GPP共享执行结果。以这种方式，GPP利用ASIP更快地执行特定应用程序/程序的能力。

4. 发明申请

US20050268144A1 Detecting a timeout of elements in an element processing system 有权
标题翻译：检测元素处理系统中元素的超时
公开(公告)号：US20050268144A1
公开(公告)日：2005-12-01
申请号：US11100157
申请日：2005-04-06
申请人： Andreas Doering , Silvio Dragone
发明人： Andreas Doering , Silvio Dragone
IPC分类号： G06F1/12 , G06F1/14
CPC分类号： G06F1/14
摘要： Provides methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, indicating a timeout interval with respect to a given time base, is assigned to each of the elements when processed. From a number of elements processed, the timer value indicating a minimum timeout interval to expire is determined out of the number of timer values assigned to the number of elements being processed.
摘要翻译：提供用于元素处理系统的定时器管理的方法，系统和装置，其中可以以时间有效的方式处理与要处理的元件相关的定时器间隔。示例性方法是用于检测元素处理系统中的元素的超时的方法，其中指示相对于给定时基的超时间隔的定时器值在被处理时被分配给每个元素。从处理的多个元素中，从分配给正在处理的元素数量的定时器值的数量中确定指示到期的最小超时间隔的定时器值。

5. 发明申请

US20050097305A1 Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
标题翻译：使用FPGA技术与微处理器进行可重配置，指令级硬件加速的方法和装置
公开(公告)号：US20050097305A1
公开(公告)日：2005-05-05
申请号：US10696865
申请日：2003-10-30
申请人： Andreas Doering , Silvio Dragone , Andreas Herkersdorf , Richard Hofmann , Charles Kuhlmann
发明人： Andreas Doering , Silvio Dragone , Andreas Herkersdorf , Richard Hofmann , Charles Kuhlmann
IPC分类号： G06F9/00 , G06F9/318 , G06F9/38 , G06F15/78
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，包括：开始处理器执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

6. 发明授权

US08140792B2 Indirectly-accessed, hardware-affine channel storage in transaction-oriented DMA-intensive environments 失效
标题翻译：在面向事务的DMA密集型环境中间接访问，硬件仿射通道存储
公开(公告)号：US08140792B2
公开(公告)日：2012-03-20
申请号：US12392282
申请日：2009-02-25
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F13/00
CPC分类号： G06F12/1081
摘要： Embodiments of the invention provide a method, system, and computer program product for managing a computer memory system including a channel controller and a memory area. In one embodiment, the method comprises the channel controller receiving a request including a header and a payload, and separating said memory area into a working memory area and an auxiliary memory area. A copy of the header is deposited in the working memory area; and a full copy of the request, including a copy of the header and a copy of the payload, is deposited in the auxiliary memory area. The copy of the request in the auxiliary memory area is used to perform hardware operations; and the copy of the header in the working memory area is used to perform software operations.
摘要翻译：本发明的实施例提供了一种用于管理包括通道控制器和存储区域的计算机存储器系统的方法，系统和计算机程序产品。在一个实施例中，该方法包括信道控制器接收包括头部和有效载荷的请求，并将所述存储区域分成工作存储器区域和辅助存储器区域。标题的副本存放在工作存储器区域中; 并且包括标题的副本和有效载荷的副本的请求的完整副本被存储在辅助存储器区域中。辅助存储器区域中的请求副本用于执行硬件操作; 并且使用工作存储器区域中的标题的副本来执行软件操作。

7. 发明授权

US08631058B2 Providing nondeterministic data 失效
标题翻译：提供非确定性数据
公开(公告)号：US08631058B2
公开(公告)日：2014-01-14
申请号：US12915003
申请日：2010-10-28
申请人： Silvio Dragone , Tamas Visegrady , Vincenzo Condorelli
发明人： Silvio Dragone , Tamas Visegrady , Vincenzo Condorelli
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H01S5/021 , H01S5/041 , H01S5/105 , H01S5/187
摘要： A system and method for providing non-deterministic data for processes executed by non-synchronized processor elements of a fault resilient system is discussed. The steps of the method comprise receiving a request for getting non-deterministic data from a requesting processor element; assigning non-deterministic data generated by an entropy source to the request; and supplying the non-deterministic data assigned to the request, to the requesting processor element.
摘要翻译：讨论了用于为故障恢复系统的非同步处理器元件执行的处理提供非确定性数据的系统和方法。所述方法的步骤包括从请求处理器元件接收获取非确定性数据的请求; 将由熵源产生的非确定性数据分配给所述请求; 以及将分配给该请求的非确定性数据提供给请求处理器元件。

8. 发明申请

US20120278905A1 CONFIGURABLE INTEGRATED TAMPER DECTECTION CIRCUITRY 失效
标题翻译：可配置集成式夯锤保护电路
公开(公告)号：US20120278905A1
公开(公告)日：2012-11-01
申请号：US13096381
申请日：2011-04-28
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F21/02
CPC分类号： G06F21/86
摘要： Tamper detection circuitry includes a first surface layer surrounding a protected memory, the first surface layer comprising a first plurality of conductive sections; a second surface layer surrounding the protected memory, the second surface layer comprising a second plurality of conductive sections; a programmable interconnect located inside the first surface layer, the programmable interconnect being connected to each conductive section by a plurality of conductive traces, the programmable interconnect being configured to group the conductive section of the first and second plurality of conductive sections into a plurality of circuits, each of the plurality of circuits having a different respective voltage; and a tamper detection module, the tamper detection module configured to detect tampering in the event that a conductive section that is part of a first circuit comes into physical contact with a conductive section that is part of a second circuit.
摘要翻译：防篡改检测电路包括围绕受保护存储器的第一表面层，第一表面层包括第一多个导电部分; 围绕被保护的存储器的第二表面层，所述第二表面层包括第二多个导电部分; 位于所述第一表面层内部的可编程互连，所述可编程互连通过多个导电迹线连接到每个导电部分，所述可编程互连配置为将所述第一和第二多个导电部分的导电部分分组成多个电路所述多个电路中的每一个具有不同的相应电压; 以及篡改检测模块，所述篡改检测模块被配置为在作为第一电路的一部分的导电部分与作为第二电路的一部分的导电部分物理接触的情况下检测篡改。

9. 发明授权

US07725591B2 Detecting a timeout of elements in an element processing system 有权
标题翻译：检测元素处理系统中元素的超时
公开(公告)号：US07725591B2
公开(公告)日：2010-05-25
申请号：US12165768
申请日：2008-07-01
申请人： Andreas Ch. Doering , Silvio Dragone
发明人： Andreas Ch. Doering , Silvio Dragone
IPC分类号： G06F15/16
CPC分类号： G06F1/14
摘要： Methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, indicating a timeout interval with respect to a given time base, is assigned to each of the elements when processed. From a number of elements processed, the timer value indicating a minimum timeout interval to expire is determined out of the number of timer values assigned to the number of elements being processed.
摘要翻译：用于元素处理系统的定时器管理的方法，系统和装置，其中可以以时间有效的方式处理与要处理的元件相关的定时器间隔。示例性方法是用于检测元素处理系统中的元素的超时的方法，其中指示相对于给定时基的超时间隔的定时器值在被处理时被分配给每个元素。从处理的多个元素中，从分配给正在处理的元素数量的定时器值的数量中确定指示到期的最小超时间隔的定时器值。

10. 发明授权

US07603540B2 Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
标题翻译：使用现场可编程门阵列（FPGA）技术与微处理器进行可重配置，指令级硬件加速
公开(公告)号：US07603540B2
公开(公告)日：2009-10-13
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F9/00 , G06F15/00
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

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