专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080270754A1 USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) TECHNOLOGY WITH A MICROPROCESSOR FOR RECONFIGURABLE, INSTRUCTION LEVEL HARDWARE ACCELERATION 有权
标题翻译：使用现场可编程门阵列（FPGA）技术与微处理器进行可重新配置，指示级硬件加速
公开(公告)号：US20080270754A1
公开(公告)日：2008-10-30
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

2. 发明授权

US07089376B2 Reducing snoop response time for snoopers without copies of requested data via snoop filtering 失效
标题翻译：通过窥探过滤减少窥探者的窥探响应时间，而无需复制所请求的数据
公开(公告)号：US07089376B2
公开(公告)日：2006-08-08
申请号：US10442485
申请日：2003-05-21
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.
摘要翻译：在具有耦合到总线宏的多个窥探主器件的系统中，在多个窥探主机中的至少一个中提供窥探过滤装置和方法。窥探过滤设备和方法解析多个窥探主机之一发出的窥探请求，并且如果解析指示所请求的数据不可能包含在响应侦听主机中，则返回立即响应。如果解析指示，否则至少一个多个窥探大师搜索其资源并且如果标记更新则返回所请求的数据。

3. 发明授权

US06993619B2 Single request data transfer regardless of size and alignment 失效
公开(公告)号：US06993619B2
公开(公告)日：2006-01-31
申请号：US10249302
申请日：2003-03-28
申请人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
发明人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
IPC分类号： G06F13/40 , H04L12/56
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.

4. 发明授权

US5557758A Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses 失效
标题翻译：计算机系统的两条总线之间的桥梁，用于确定其中一条总线上的存储器位置或从总线主站访问
公开(公告)号：US5557758A
公开(公告)日：1996-09-17
申请号：US351192
申请日：1994-11-30
申请人： Patrick M. Bland , Richard G. Hofmann , Sagi Katz , Dennis Moeller , Lance M. Venarchick
发明人： Patrick M. Bland , Richard G. Hofmann , Sagi Katz , Dennis Moeller , Lance M. Venarchick
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.
摘要翻译：在工业标准架构（ISA）总线和外围控制器互连（PCI）总线之间提供一个桥，并且当ISA总线上的主机启动存储器传输时，同时在两个总线上执行存储器周期。当PCI总线上的从站在PCI总线上启动存储器周期之后的预定时间段内，PCI总线上的从站要求存储器地址时，在ISA和PCI总线之间转移数据。当PCI总线上的从站不占用内存地址时，ISA总线与PCI总线隔离。这允许在ISA总线上完成存储器周期，PCI总线上的存储器周期终止。

5. 发明授权

US5548786A Dynamic bus sizing of DMA transfers 失效
标题翻译： DMA传输的动态总线大小
公开(公告)号：US5548786A
公开(公告)日：1996-08-20
申请号：US224123
申请日：1994-04-06
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
IPC分类号： G06F13/28 , G06F13/00 , G06F13/40
CPC分类号： G06F13/28
摘要： A DMA controller is provided for transferring data between source and destination devices over an I/O bus. The DMA control circuit includes a bus interface unit for providing a bus size information at the beginning of each consecutive bus cycle and a look ahead responsive to the bus size information for providing a bus size control signal. A DMA control circuit responsive to the bus size control signal controls the bus width during contiguous transfer cycles. By dynamically adjusting the DMA control circuit, back to back data reads and writes may occur with no wait states inserted for generating the terminal count information.
摘要翻译：提供DMA控制器用于通过I / O总线在源设备和目标设备之间传输数据。 DMA控制电路包括总线接口单元，用于在每个连续的总线周期的开始处提供总线尺寸信息，并且响应于总线尺寸信息提供前视，用于提供总线尺寸控制信号。响应于总线尺寸控制信号的DMA控制电路在连续传送周期期间控制总线宽度。通过动态调整DMA控制电路，背靠背数据读取和写入可能会在没有插入等待状态以产生终端计数信息的情况下进行。

6. 发明授权

US5396602A Arbitration logic for multiple bus computer system 失效
标题翻译：多总线计算机系统的仲裁逻辑
公开(公告)号：US5396602A
公开(公告)日：1995-03-07
申请号：US69253
申请日：1993-05-28
申请人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Richard G. Hofmann , Terence J. Lohman
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
CPC分类号： G06F13/364 , G06F13/4031
摘要： An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.
摘要翻译：提供了一种在计算机系统中使用的仲裁机制，其包括（i）中央处理单元（CPU）; （ii）第一系统总线，其将CPU连接到系统存储器，使得CPU可以从系统存储器读取数据并将数据写入系统存储器; （iii）连接到CPU的第二系统总线; （iv）将所述第二系统总线连接到外围总线的主桥，所述外围总线具有附接到其上的至少一个外围设备; 以及（v）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，所述标准I / O总线具有附接到其上的多个标准I / O设备。仲裁机制包括（i）用于在多个标准I / O设备之间进行仲裁的第一级逻辑，其中从多个标准I / O设备中选择一个标准I / O设备来竞争访问标准I / O总线，以及（ii）用于在所选择的标准I / O设备，CPU和至少一个外围设备之间进行仲裁的第二级逻辑，其中所选择的标准I / O设备，CPU和at 选择至少一个外围设备来访问外围总线。仲裁机制包括连接第一级仲裁逻辑和第二级仲裁逻辑的边带信号，并包括对应于所选标准I / O设备的仲裁识别信息。

7. 发明授权

US08599886B2 Methods and apparatus for reducing transfer qualifier signaling on a two-channel bus 有权
标题翻译：用于减少双通道总线上传输限定符信令的方法和装置
公开(公告)号：US08599886B2
公开(公告)日：2013-12-03
申请号：US12868814
申请日：2010-08-26
申请人： Martyn R. Shirlen , Richard G. Hofmann , Mark M. Schaffer
发明人： Martyn R. Shirlen , Richard G. Hofmann , Mark M. Schaffer
IPC分类号： H04J3/12
CPC分类号： G06F13/4273 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.
摘要翻译：为了促进与多个外围设备通信的多总线主系统中的有效通信，使用两个通道总线，其在发送信道上共享具有数据的写入和读取地址以降低布线密度并提供有效，可靠和高速度数据传输。双通道总线包括发送通道，接收通道和单个控制通道，其为发送通道和接收通道两者提供控制信息，进一步减少了双通道总线的信令要求。控制信息包括指定用于在两个信道总线上进行数据传输的控制信息的控制标志。控制标志和控制信息可以在两个总线周期或单个总线周期中提供，这取决于在两个通道总线上并行发生的两次数据传输的控制要求。

8. 发明申请

US20120051373A1 Methods and Apparatus for Reducing Transfer Qualifier Signaling on a Two-Channel Bus 有权
标题翻译：用于减少双通道总线上的传输限定符信令的方法和装置
公开(公告)号：US20120051373A1
公开(公告)日：2012-03-01
申请号：US12868814
申请日：2010-08-26
申请人： Martyn R. Shirlen , Richard G. Hofmann , Mark M. Schaffer
发明人： Martyn R. Shirlen , Richard G. Hofmann , Mark M. Schaffer
IPC分类号： H04J3/00
CPC分类号： G06F13/4273 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.
摘要翻译：为了促进与多个外围设备通信的多总线主系统中的有效通信，使用两个通道总线，其在发送信道上共享具有数据的写入和读取地址以降低布线密度并提供有效，可靠和高速度数据传输。双通道总线包括发送通道，接收通道和单个控制通道，其为发送通道和接收通道两者提供控制信息，进一步减少了双通道总线的信令要求。控制信息包括指定用于在两个信道总线上进行数据传输的控制信息的控制标志。控制标志和控制信息可以在两个总线周期或单个总线周期中提供，这取决于在两个通道总线上并行发生的两次数据传输的控制要求。

9. 发明授权

US07685373B2 Selective snooping by snoop masters to locate updated data 失效
标题翻译：通过窥探大师进行选择性窥探以查找更新的数据
公开(公告)号：US07685373B2
公开(公告)日：2010-03-23
申请号：US11970599
申请日：2008-01-08
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译：一种用于窥探连接到总线宏的多个窥探主机的高速缓存存储器的系统和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但不到全部高速缓冲存储器可具有始发请求的数据窥探主机，其中在非始发侦听主机中所需的数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。只有那些可能具有请求的数据的非始发侦听主机才被查询。所有被查询的非始发侦听主人都回复。如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

10. 发明授权

US5642489A Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management 失效
标题翻译：具有计算机系统的两条总线之间的桥梁，具有可访问寄存器的直接存储器访问控制器，以支持电源管理
公开(公告)号：US5642489A
公开(公告)日：1997-06-24
申请号：US359330
申请日：1994-12-19
申请人： Patrick Maurice Bland , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
发明人： Patrick Maurice Bland , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
IPC分类号： G06F1/32 , G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F1/3225 , G06F13/28 , G06F13/4027
摘要： A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer. The DMA has registers for storing base addresses and registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A power management device is coupled to the DMA control circuit and has logic for causing the computer system to enter a suspend mode. A base address register read circuit is coupled to the base address registers. Prior to entering the suspend mode, the base address register read circuit provides one of the base addresses to be read by a central processing unit (CPU) onto disk storage. When the power management device resumes operation of the computer system, the base address that has been read is written back to reprogram the DMA control circuit. The ability to read the base address registers and store base addresses allows a reduction or elimination of shadow registers that shadow every write to a base address register.
摘要翻译：用于在具有工业标准架构（ISA）总线和外围控制器互连（PCI）总线的计算机系统中连接总线的桥耦合在ISA和PCI总线之间。该桥具有通过编程信号可编程的直接存储器存取（DMA）控制电路，以执行DMA传输。 DMA具有用于存储用于存储当前地址的基地址和寄存器的寄存器。基地址和当前地址表示DMA传输中传输数据的目的地。电源管理设备耦合到DMA控制电路，并且具有使计算机系统进入挂起模式的逻辑。基地址寄存器读电路耦合到基地址寄存器。在进入暂停模式之前，基地址寄存器读取电路提供要由中央处理单元（CPU）读取到磁盘存储器上的基地址之一。当电源管理设备恢复计算机系统的操作时，将读取的基地址写回DMA控制电路。读取基地址寄存器和存储基地址的能力允许减少或消除阴影寄存器，从而影响每个对基地址寄存器的写入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式