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1. 发明授权

US08660173B2 Video reference frame retrieval 有权
标题翻译：视频参考帧检索
公开(公告)号：US08660173B2
公开(公告)日：2014-02-25
申请号：US12923797
申请日：2010-10-07
申请人： Andreas Björklund , Erik Persson , Pontus Borg , Mats Petter Wallander
发明人： Andreas Björklund , Erik Persson , Pontus Borg , Mats Petter Wallander
IPC分类号： H04B1/66
CPC分类号： H04N19/423 , H04N19/61
摘要： A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames.
摘要翻译：提供了一种视频数据处理装置，包括用于执行需要访问视频参考帧的视频处理操作的处理电路，以及被配置为将虚拟地址转换成物理地址的存储器管理单元。提供翻译电路，其响应于由处理电路发出的参考帧像素数据的存储器访问请求，以执行对视频参考帧信息的转换处理，使得存储器管理单元中的至少一个散列函数的输入值集合包括视频包含在视频参考帧信息中的参考帧标识符位。已经发现这种方法在检索视频参考帧时降低存储器管理单元中的混叠频率。

2. 发明申请

US20110080959A1 Video reference frame retrieval 有权
标题翻译：视频参考帧检索
公开(公告)号：US20110080959A1
公开(公告)日：2011-04-07
申请号：US12923797
申请日：2010-10-07
申请人： Andreas Björklund , Erik Persson , Pontus Borg , Mats Petter Wallander
发明人： Andreas Björklund , Erik Persson , Pontus Borg , Mats Petter Wallander
IPC分类号： H04N5/14 , H04N7/26
CPC分类号： H04N19/423 , H04N19/61
摘要： A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames.
摘要翻译：提供了一种视频数据处理装置，包括用于执行需要访问视频参考帧的视频处理操作的处理电路，以及被配置为将虚拟地址转换成物理地址的存储器管理单元。提供翻译电路，其响应于由处理电路发出的参考帧像素数据的存储器访问请求，以执行对视频参考帧信息的转换处理，使得存储器管理单元中的至少一个散列函数的输入值集合包括视频包含在视频参考帧信息中的参考帧标识符位。已经发现这种方法在检索视频参考帧时降低存储器管理单元中的混叠频率。

3. 发明授权

US08473717B2 Coprocessor reset controller with queue for storing configuration information of subsequent sessions prior to completion of current session 有权
标题翻译：具有队列的协处理器复位控制器，用于在当前会话完成之前存储后续会话的配置信息
公开(公告)号：US08473717B2
公开(公告)日：2013-06-25
申请号：US12656570
申请日：2010-02-03
申请人： Ola Hugosson , Erik Persson , Pontus Borg
发明人： Ola Hugosson , Erik Persson , Pontus Borg
IPC分类号： G06F9/40
CPC分类号： G06F9/06 , G06F12/08 , G06F12/10 , G06F13/00 , G06F15/76
摘要： A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data.
摘要翻译：提供了一种数据处理装置，其被配置为代表主数据处理装置执行数据处理操作，所述主数据处理装置包括被配置为执行数据处理操作的协处理器核心和被配置为使协处理器核复位的复位控制器。协处理器内核根据存储在其中的当前配置数据执行其数据处理，当前配置数据与当前处理会话相关联。复位控制器被配置为从主数据处理设备接收待处理的配置数据，与待处理的处理会话相关联的未决配置数据，以及将未决配置数据存储在配置数据队列中。配置复位控制器，当协处理器内核复位时，将待配置数据从配置数据队列传输到存储在协处理器内核中，替换当前配置数据。

4. 发明申请

US20110191539A1 Coprocessor session switching 有权
标题翻译：协处理器会话切换
公开(公告)号：US20110191539A1
公开(公告)日：2011-08-04
申请号：US12656570
申请日：2010-02-03
申请人： Ola Hugosson , Erik Persson , Pontus Borg
发明人： Ola Hugosson , Erik Persson , Pontus Borg
IPC分类号： G06F15/76 , G06F9/06 , G06F12/10 , G06F12/08 , G06F13/00
CPC分类号： G06F9/06 , G06F12/08 , G06F12/10 , G06F13/00 , G06F15/76
摘要： A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data.
摘要翻译：提供了一种数据处理装置，其被配置为代表主数据处理装置执行数据处理操作，包括被配置为执行数据处理操作的协处理器核心和被配置为使协处理器核心复位的复位控制器。协处理器内核根据存储在其中的当前配置数据执行其数据处理，当前配置数据与当前处理会话相关联。复位控制器被配置为从主数据处理设备接收待处理的配置数据，与待处理的处理会话相关联的未决配置数据，以及将未决配置数据存储在配置数据队列中。配置复位控制器，当协处理器内核复位时，将待配置数据从配置数据队列传输到存储在协处理器内核中，替换当前配置数据。

5. 发明申请

US20110087858A1 Memory management unit 有权
标题翻译：内存管理单元
公开(公告)号：US20110087858A1
公开(公告)日：2011-04-14
申请号：US12588263
申请日：2009-10-08
申请人： Erik Persson , Ola Hugosson , Andreas Björklund
发明人： Erik Persson , Ola Hugosson , Andreas Björklund
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1018 , G06F12/1027 , G06F12/122
摘要： A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.
摘要翻译：提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。因此避免了主设备在使用内部存储单元时的冲突。

6. 发明授权

US08924686B2 Memory management unit 有权
标题翻译：内存管理单元
公开(公告)号：US08924686B2
公开(公告)日：2014-12-30
申请号：US12588263
申请日：2009-10-08
申请人： Erik Persson , Ola Hugosson , Andreas Björklund
发明人： Erik Persson , Ola Hugosson , Andreas Björklund
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34 , G06F12/10
CPC分类号： G06F12/1018 , G06F12/1027 , G06F12/122
摘要： A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.
摘要翻译：提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。因此避免了主设备在使用内部存储单元时的冲突。

7. 发明授权

US08661225B2 Data processing apparatus and method for handling vector instructions 有权
标题翻译：用于处理向量指令的数据处理装置和方法
公开(公告)号：US08661225B2
公开(公告)日：2014-02-25
申请号：US12656152
申请日：2010-01-19
申请人： Andreas Björklund , Erik Persson , Ola Hugosson
发明人： Andreas Björklund , Erik Persson , Ola Hugosson
IPC分类号： G06F15/00
CPC分类号： G06F9/30072 , G06F9/30036 , G06F9/30069 , G06F9/3887
摘要： A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes. The vector processing unit is responsive to a vector operation instruction to perform an operation in parallel on data elements input to the plurality of lanes of parallel processing, but to exclude from the performance of the operation any lane whose associated skip indicator is set. This allows the operation specified by vector instructions to be performed conditionally within each of the lanes of parallel processing without any modification to the vector instructions that are specifying those operations.
摘要翻译：一种用于处理向量指令的数据处理装置和方法。数据处理装置具有寄存器数据存储器，其具有多个用于存储数据元素的寄存器。然后，矢量处理单元用于执行矢量指令序列，其中矢量处理单元具有多个并行处理通道，并且能够访问寄存器数据存储器，以便从数据元素读取数据元素，在执行向量指令序列期间的寄存器数据存储。跳过指示存储保持每个并行处理通道的跳过指示符。向量处理单元响应于向量跳过指令执行更新操作，以在跳过指示存储内设置用于所确定的一个或多个车道的跳过指示符。向量处理单元响应于矢量操作指令，并行地对输入到多个并行处理通道的数据元素执行操作，但是从执行操作排除任何相关联的跳过指示符被设置的通道。这允许在并行处理的每个通道内有条件地执行由向量指令指定的操作，而不对指定这些操作的向量指令进行任何修改。

8. 发明授权

US08375196B2 Vector processor with vector register file configured as matrix of data cells each selecting input from generated vector data or data from other cell via predetermined rearrangement path 有权
标题翻译：向量处理器，其向量寄存器文件被配置为数据单元的矩阵，每个数据单元通过预定的重排路径从产生的矢量数据或来自其它单元的数据中选择输入
公开(公告)号：US08375196B2
公开(公告)日：2013-02-12
申请号：US12656156
申请日：2010-01-19
申请人： Andreas Björklund , Erik Persson , Ola Hugosson
发明人： Andreas Björklund , Erik Persson , Ola Hugosson
IPC分类号： G06F17/16
CPC分类号： G06F9/30141 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3826 , G06F9/3836
摘要： A data processing apparatus includes a vector register bank having a plurality of vector registers, each register including a plurality of storage cells, each cell storing a data element. A vector processing unit is provided for executing a sequence of vector instructions. The processing unit is arranged to issue a set rearrangement enable signal to the vector register bank. The write interface of the vector register bank is modified to provide not only a first input for receiving the data elements generated by the vector processing unit during normal execution, but also has a second input coupled via a data rearrangement path to the matrix of storage cells via which the data elements currently stored in the matrix of storage cells are provided to the write interface in a rearranged form representing the arrangement of data elements that would be obtained by performance of the predetermined rearrangement operation.
摘要翻译：数据处理装置包括具有多个向量寄存器的向量寄存器组，每个寄存器包括多个存储单元，每个单元存储数据元素。提供了用于执行向量指令序列的向量处理单元。处理单元被布置成向向量寄存器组发出一个置位重排使能信号。修改向量寄存器组的写接口，不仅提供用于在正常执行期间接收由向量处理单元生成的数据元素的第一输入，还具有经由数据重排路径耦合到存储单元矩阵的第二输入通过其将当前存储在存储单元的矩阵中的数据元素以重新排列的形式提供给写入接口，表示通过执行预定重新排列操作将获得的数据元素的布置。

9. 发明申请

US20100313060A1 Data processing apparatus and method for performing a predetermined rearrangement operation 有权
标题翻译：用于执行预定重排动作的数据处理装置和方法
公开(公告)号：US20100313060A1
公开(公告)日：2010-12-09
申请号：US12656156
申请日：2010-01-19
申请人： Andreas Björklund , Erik Persson , Ola Hugosson
发明人： Andreas Björklund , Erik Persson , Ola Hugosson
IPC分类号： G06F15/76 , G06F9/06 , G06F1/04
CPC分类号： G06F9/30141 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3826 , G06F9/3836
摘要： A data processing apparatus and method are provided for performing a predetermined rearrangement operation. The data processing apparatus comprises a vector register bank having a plurality of vector registers, with each vector register comprising a plurality of storage cells such that the plurality of vector registers provide a matrix of storage cells. Each storage cell is arranged to store a data element. A vector processing unit is provided for executing a sequence of vector instructions in order to apply operations to the data elements held in the vector register bank. Responsive to a vector matrix rearrangement instruction specifying a predetermined rearrangement operation to be performed on the data elements in the matrix of storage cells, the vector processing unit is arranged to issue a set rearrangement enable signal to the vector register bank. The write interface of the vector register bank is modified to provide not only a first input for receiving the data elements generated by the vector processing unit during normal execution, but also has a second input coupled via a data rearrangement path to the matrix of storage cells via which the data elements currently stored in the matrix of storage cells are provided to the write interface in a rearranged form representing the arrangement of data elements that would be obtained by performance of the predetermined rearrangement operation. When the rearrangement enable signal is set, the write interface then performs a write operation to the storage cells of the matrix using the data elements received at the second input. This enables the predetermined rearrangement operation to be performed at high speed and with significantly less complexity than in prior art systems.
摘要翻译：提供了一种用于执行预定重排动作的数据处理装置和方法。数据处理装置包括具有多个向量寄存器的向量寄存器组，每个向量寄存器包括多个存储单元，使得多个向量寄存器提供存储单元矩阵。每个存储单元被布置成存储数据元素。向量处理单元被提供用于执行向量指令序列，以便将操作应用于保持在向量寄存器组中的数据元素。响应于指定对存储单元矩阵中的数据元素执行的预定重排操作的向量矩阵重排指令，向量处理单元被布置为向向量寄存器组发出置位重排使能信号。修改向量寄存器组的写接口，不仅提供用于在正常执行期间接收由向量处理单元生成的数据元素的第一输入，还具有经由数据重排路径耦合到存储单元矩阵的第二输入通过其将当前存储在存储单元的矩阵中的数据元素以重新排列的形式提供给写入接口，表示通过执行预定重新排列操作将获得的数据元素的布置。当重新布置使能信号被设置时，写入接口然后使用在第二输入端接收到的数据元素对矩阵的存储单元进行写入操作。这使得能够以比现有技术的系统更高的速度和更小的复杂度执行预定的重新排列操作。

10. 发明申请

US20100312988A1 Data processing apparatus and method for handling vector instructions 有权
标题翻译：用于处理向量指令的数据处理装置和方法
公开(公告)号：US20100312988A1
公开(公告)日：2010-12-09
申请号：US12656152
申请日：2010-01-19
申请人： Andreas BJÖRKLUND , Erik Persson , Ola Hugosson
发明人： Andreas BJÖRKLUND , Erik Persson , Ola Hugosson
IPC分类号： G06F15/00
CPC分类号： G06F9/30072 , G06F9/30036 , G06F9/30069 , G06F9/3887
摘要： A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes. The vector processing unit is responsive to a vector operation instruction to perform an operation in parallel on data elements input to the plurality of lanes of parallel processing, but to exclude from the performance of the operation any lane whose associated skip indicator is set. This allows the operation specified by vector instructions to be performed conditionally within each of the lanes of parallel processing without any modification to the vector instructions that are specifying those operations.
摘要翻译：一种用于处理向量指令的数据处理装置和方法。数据处理装置具有寄存器数据存储器，其具有多个用于存储数据元素的寄存器。然后，矢量处理单元用于执行矢量指令序列，其中矢量处理单元具有多个并行处理通道，并且能够访问寄存器数据存储器，以便从数据元素读取数据元素，在执行向量指令序列期间的寄存器数据存储。跳过指示存储保持每个并行处理通道的跳过指示符。向量处理单元响应于向量跳过指令执行更新操作，以在跳过指示存储内设置用于所确定的一个或多个车道的跳过指示符。向量处理单元响应于矢量操作指令，并行地对输入到多个并行处理通道的数据元素执行操作，但是从执行操作排除任何相关联的跳过指示符被设置的通道。这允许在并行处理的每个通道内有条件地执行由向量指令指定的操作，而不对指定这些操作的向量指令进行任何修改。

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