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1. 发明授权

US07310058B2 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) 有权
标题翻译：减少将模拟输入采样转换为模拟数字转换器（ADC）中数字码的时间，
公开(公告)号：US07310058B2
公开(公告)日：2007-12-18
申请号：US11160859
申请日：2005-07-13
申请人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvaraya A. Pentakota , Sandeep Oswal
发明人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvaraya A. Pentakota , Sandeep Oswal
IPC分类号： H03M1/38
CPC分类号： H03M1/168
摘要： A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
摘要翻译：流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC，减法器和放大）。由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

2. 发明授权

US07576668B2 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) 有权
标题翻译：减少将模拟输入采样转换为模拟数字转换器（ADC）中数字码的时间，
公开(公告)号：US07576668B2
公开(公告)日：2009-08-18
申请号：US11934611
申请日：2007-11-02
申请人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvararaya A. Pentakota , Sandeep Oswal
发明人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvararaya A. Pentakota , Sandeep Oswal
IPC分类号： H03M1/00
CPC分类号： H03M1/168
摘要： A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
摘要翻译：流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC，减法器和放大）。由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

3. 发明申请

US20070013569A1 Reducing the Time to Convert an Analog Input Sample to a Digital Code in an analog to digital converter (ADC) 有权
标题翻译：减少模拟输入采样到模拟数字转换器（ADC）中的数字代码的时间
公开(公告)号：US20070013569A1
公开(公告)日：2007-01-18
申请号：US11160859
申请日：2005-07-13
申请人： Anand Udupa , Vikas Sinha , Nitin Agarwal , Visvesvaraya PENTAKOTA , Sandeep Oswal
发明人： Anand Udupa , Vikas Sinha , Nitin Agarwal , Visvesvaraya PENTAKOTA , Sandeep Oswal
IPC分类号： H03M1/12
CPC分类号： H03M1/168
摘要： A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
摘要翻译：流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC，减法器和放大）。由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

4. 发明申请

US20080055129A1 REDUCING THE TIME TO CONVERT AN ANALOG INPUT SAMPLE TO A DIGITAL CODE IN AN ANALOG TO DIGITAL CONVERTER (ADC) 有权
标题翻译：将模拟输入示例转换为数字转换器（ADC）的模拟数字代码的时间缩短
公开(公告)号：US20080055129A1
公开(公告)日：2008-03-06
申请号：US11934611
申请日：2007-11-02
申请人： Anand Udupa , Vikas Sinha , Nitin Agarwal , Visvesvararaya Pentakota , Sandeep Oswal
发明人： Anand Udupa , Vikas Sinha , Nitin Agarwal , Visvesvararaya Pentakota , Sandeep Oswal
IPC分类号： H03M1/12
CPC分类号： H03M1/168
摘要： A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
摘要翻译：流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC，减法器和放大）。由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

5. 发明申请

US20070182456A1 Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form 审中-公开
标题翻译：当数字输出以差分或单端形式提供时，减少引脚数
公开(公告)号：US20070182456A1
公开(公告)日：2007-08-09
申请号：US11561424
申请日：2006-11-20
申请人： Nitin Agarwal , Eduardo Bartolome , Sandeep Oswal , Visvesvaraya Pentakota , Jagannathan Venkataraman , Nagarajan Viswanathan , Vinod Paliakara
发明人： Nitin Agarwal , Eduardo Bartolome , Sandeep Oswal , Visvesvaraya Pentakota , Jagannathan Venkataraman , Nagarajan Viswanathan , Vinod Paliakara
IPC分类号： H03K19/00
CPC分类号： H03K19/1732
摘要： An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form (single-ended or differential) of outputs are being provided, outputs in the other form are disabled. Outputs in differential form may be provided at twice the frequency as compared to the outputs in single-ended form. As a result the same number of pins can be supported for both single-ended and differential outputs for a desired data throughput, and the pin count of the integrated circuit is reduced.
摘要翻译：集成电路在共享引脚组上提供单端或差分形式的数字输出信号。控制电路产生信号，以确保当提供输出的一个形式（单端或差分）时，另一种形式的输出被禁用。与单端形式的输出相比，差分形式的输出可以提供两倍的频率。因此，为了达到所需的数据吞吐量，单端和差分输出都可以支持相同数量的引脚，并且减少了集成电路的引脚数。

6. 发明申请

US20060114141A1 A Novel Multi-stage Analog to Digital Converter Architecture 有权
标题翻译：一种新型多级模数转换器架构
公开(公告)号：US20060114141A1
公开(公告)日：2006-06-01
申请号：US11161211
申请日：2005-07-27
申请人： Gautam Nandi , Visvesvaraya Pentakota , Nitin Agarwal , Sandeep Oswal
发明人： Gautam Nandi , Visvesvaraya Pentakota , Nitin Agarwal , Sandeep Oswal
IPC分类号： H03M1/12
CPC分类号： H03M1/167 , H03M1/002
摘要： According to an aspect of the present invention, different reference voltage levels are used for different stages of a multi-stage analog to digital converter (ADC). In one embodiment, the amplification and unity gain bandwidth (UGB) requirements in the first stage is reduced as a result.
摘要翻译：根据本发明的一个方面，不同的参考电压电平用于多级模数转换器（ADC）的不同级。在一个实施例中，结果是降低了第一级中的放大和单位增益带宽（UGB）要求。

7. 发明授权

US07023929B2 Digital pre-compensation filter for DMT type transmitter 有权
标题翻译： DMT型变送器数字预补偿滤波器
公开(公告)号：US07023929B2
公开(公告)日：2006-04-04
申请号：US10191994
申请日：2002-07-10
申请人： Fernando A. Mujica , Udayan Dasgupta , Mangesh Sadafale , Sandeep Oswal , Prakash Easwaran
发明人： Fernando A. Mujica , Udayan Dasgupta , Mangesh Sadafale , Sandeep Oswal , Prakash Easwaran
IPC分类号： H04K1/10
CPC分类号： H04L27/367 , H04L27/2626
摘要： A method of providing an improved transfer function for a Discrete Multitone (DMT) type modulation transmitter with digital filtering after modulation followed by digital to analog converter and analog filtering is provided by sending a test signal to said transmitter and measuring the results of the test signal to determine the transfer function. The inverse of the transfer function that needs to be compensated is determined and the inverse of transfer function to be compensated is truncated to the region of interest (H2). The desired band split component of pre-compensation filter is designed (H3). The desired target frequency response of the pre-compensation filter is determined by H4=H2*H3 where H4 is the multiplication of H2 and H3 Given the target frequency response in H4 Hermetian symmetry is imposed on the frequency response. The inverse Fourier transform (IFFT) is taken to generate a time domain filter, h5. The characteristic of this filter is added at the digital filtering after modulation.
摘要翻译：通过向所述发射机发送测试信号并测量测试信号的结果，提供一种为调制后的数字滤波后的数模转换器和模拟滤波器为离散多音（DMT）型调制发射机提供改进的传递函数的方法确定传递函数。确定需要补偿的传递函数的逆，并且要补偿的传递函数的逆被截断到感兴趣的区域（H 2> 2）。设计了预补偿滤波器的期望频带分离分量（H 3 3 3）。预补偿滤波器的期望目标频率响应由H 4 = H 2 / H 3 3 H 3确定，其中H 4 < 假定在H 4中的目标频率响应，Hermetian对称性被施加在频率响应上，则/ SUB>是H 2 2和H 3 3的乘法。采用逆傅里叶变换（IFFT）来产生时域滤波器h 5。该滤波器的特性在调制后的数字滤波中相加。

8. 发明授权

US06831975B1 Digital subscriber line (DSL) modem compatible with home networks 有权
标题翻译：与家庭网络兼容的数字用户线（DSL）调制解调器
公开(公告)号：US06831975B1
公开(公告)日：2004-12-14
申请号：US09661629
申请日：2000-09-13
申请人： Prakash Easwaran , Sandeep Oswal
发明人： Prakash Easwaran , Sandeep Oswal
IPC分类号： H04M100
CPC分类号： H04L27/0002 , H03H11/1217 , H03H11/1252 , H04L5/14 , H04L27/2647
摘要： A cost-effective filter consuming low power and occupying minimal space. The filter may be used in a ADSL modem (or CPE) to filter the signal components other than the ADSL signals. A high pass filter first filters the low frequency components to attenuate (or remove) lower frequency components such as that caused by ADSL transmit echo signals and that used for voice transmission. The high pass filter may be modified by adding a few resistors to limit the voltages of the high frequency signals also. The output of the high pass filter is amplified and passed through a low pass filter to filter the high frequency components (HPNA included). Due to earlier filtering operation of the high pass filter, the signal can be amplified substantially before being sent to the low pass filter. The implementation of the low pass filter is simplified due to the prior amplification.
摘要翻译：消耗低功耗且占用最小空间的成本效益过滤器。该滤波器可用于ADSL调制解调器（或CPE）中以对除ADSL信号之外的信号分量进行滤波。高通滤波器首先对低频分量进行滤波，以衰减（或去除）较低频率的分量，例如由ADSL发射回波信号和用于语音传输的频率成分。高通滤波器可以通过添加几个电阻器来修改，以限制高频信号的电压。高通滤波器的输出被放大并通过低通滤波器以过滤高频分量（包括HPNA）。由于高通滤波器的较早的滤波操作，可以在发送到低通滤波器之前基本上放大该信号。由于先前的放大，低通滤波器的实现被简化。

9. 发明授权

US07885144B2 Time-dependant gain control for an amplifier used in receiving echoes 有权
标题翻译：用于接收回波的放大器的时间依赖增益控制
公开(公告)号：US07885144B2
公开(公告)日：2011-02-08
申请号：US12241075
申请日：2008-09-30
申请人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
发明人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
IPC分类号： G01S15/00
CPC分类号： G01S7/52033
摘要： An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.
摘要翻译：放大器电路，用于放大回波序列并产生相应的放大信号序列。在一个实施例中，放大器包括具有可变输入和反馈电阻的运算放大器，使得可以控制两个电阻的比率。增益控制块以时间依赖的方式控制比率，以获得每个回波的期望的增益因子。可以预先计算增益因子，使得在超声系统的情况下，所有回波都被获得到相同的水平。

10. 发明授权

US07298207B2 Automatic gain control for a multi-stage gain system 有权
标题翻译：多级增益系统的自动增益控制
公开(公告)号：US07298207B2
公开(公告)日：2007-11-20
申请号：US10966981
申请日：2004-10-15
申请人： Susan Yim , Udayan Dasgupta , Sandeep Oswal , Murtaza Ali
发明人： Susan Yim , Udayan Dasgupta , Sandeep Oswal , Murtaza Ali
IPC分类号： H03F3/04 , H03F3/68
CPC分类号： H03G3/001 , H03G1/0088 , H03G3/3036
摘要： Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.
摘要翻译：公开了用于提供多级系统的自动增益控制的系统和方法。一种方法可以包括定义至少一个适于至少一个参数的参数，其中最小化多个增益级中的每一个的硬件容量并减轻多级系统的部分变化。选择用于基于多个级的相对噪声优势来训练多个级的顺序。对于根据所选择的顺序选择的多个级的给定级，在给定级的多个增益设置上测量多级系统的输出信号。基于相对于为给定阶段定义的至少一个参数的测量输出信号，配置多级系统的给定级的增益设置。多个增益级可以包括串联连接的模拟均衡器以及可编程增益放大器。

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