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1. 发明授权

US07969334B2 Apparatus for correcting setting error in an MDAC amplifier 有权
标题翻译：用于校正MDAC放大器设置误差的装置
公开(公告)号：US07969334B2
公开(公告)日：2011-06-28
申请号：US12645220
申请日：2009-12-22
申请人： Ganesh Kiran , Visvesvaraya A. Pentakota
发明人： Ganesh Kiran , Visvesvaraya A. Pentakota
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/167 , H03M1/66
摘要： Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capacitor network that compensates for this settling error. Thus, a more accurate pipelined ADC can now be produced.
摘要翻译：通常在流水线模数转换器（ADC）中采用的乘法数字模拟转换器（MDAC）可能会产生与MDAC放大器相关的稳定误差。这里提供了一个电路，其中包括额外的放大器和补偿该稳定误差的电容器网络。因此，现在可以生产更精确的流水线ADC。

2. 发明申请

US20090135037A1 Correcting Offset Errors Associated With A Sub-ADC In Pipeline Analog To Digital Converters 有权
标题翻译：纠正与管道模拟数字转换器中的子ADC相关的偏移误差
公开(公告)号：US20090135037A1
公开(公告)日：2009-05-28
申请号：US11945278
申请日：2007-11-27
申请人： Nitin Agarwal , Ramesh Kumar Singh , Visvesvaraya A. Pentakota , Dantes John , Supreet Joshi
发明人： Nitin Agarwal , Ramesh Kumar Singh , Visvesvaraya A. Pentakota , Dantes John , Supreet Joshi
IPC分类号： H03M3/00
CPC分类号： H03M1/1023 , H03M1/0607 , H03M1/0624 , H03M1/167 , H03M1/362
摘要： An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
摘要翻译：偏移校正电路检查管线模数转换器（ADC）的级的残留信号，以确定是否需要调整可能导致偏移误差的参数。在一个实施例中，调整参数直到残差信号的最大范围等于预期范围。在所描述的示例中，经调整的参数包括定时偏移误差（当ADC的分量对不同时间的输入信号进行采样时）和电压偏移误差（在产生子码的阶段中的子ADC的阈值电压更改为下一个值）。

3. 发明授权

US06906658B2 Reducing droop in a reference signal provided to ADCs 有权
标题翻译：减少提供给ADC的参考信号中的下垂
公开(公告)号：US06906658B2
公开(公告)日：2005-06-14
申请号：US10708853
申请日：2004-03-29
申请人： Visvesvaraya A. Pentakota , Gautam Salil Nandi
发明人： Visvesvaraya A. Pentakota , Gautam Salil Nandi
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03M1/0607 , H03M1/12
摘要： An aspect of the present invention reduces droop in the reference signal provided to ADCs. A compensation resistor of appropriate resistance value is provided in the path of the reference signal to minimize the droop.
摘要翻译：本发明的一个方面减小提供给ADC的参考信号中的下垂。在参考信号的路径中提供具有适当电阻值的补偿电阻，以使下垂最小化。

4. 发明申请

US20110204930A1 SOURCE FOLLOWER INPUT BUFFER 有权
公开(公告)号：US20110204930A1
公开(公告)日：2011-08-25
申请号：US12763945
申请日：2010-04-20
申请人： Nitin Agarwal , Visvesvaraya A. Pentakota
发明人： Nitin Agarwal , Visvesvaraya A. Pentakota
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , G11C27/024
摘要： Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.
摘要翻译：传统上，模数转换器（ADC）的输入源跟随缓冲器缺乏足够高的线性度。这是由于源极跟随缓冲器必须通过向容性负载提供信号电流来驱动外部电容性负载。这里提供了缓冲器，其包括源极跟随器缓冲器和其它偏置电路（其提供信号电流）。因此，输入电路（即，输入缓冲器）的整体线性度得到改善。

5. 发明授权

US07948410B2 Multibit recyclic pipelined ADC architecture 有权
标题翻译：多位循环流水线ADC结构
公开(公告)号：US07948410B2
公开(公告)日：2011-05-24
申请号：US12639705
申请日：2009-12-16
申请人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
发明人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
IPC分类号： H03M1/00
CPC分类号： H03M1/0695 , H03M1/167
摘要： An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
摘要翻译：提供了一种装置。该装置包括采样开关，采样电容器，放大器，反馈分支，第二保持开关，N位转换器对，第三保持开关和M位转换器对。样本接收输入信号并由样本信号启动。采样电容器耦合到采样开关。放大器具有耦合到采样电容器的第一输入端。反馈支路耦合在放大器的输出端和放大器的第一输入端之间，每个反馈支路包括反馈电容器，以及耦合到反馈电容器的第一保持开关。第二保持开关耦合到采样开关。 N位转换器对耦合到采样开关和第二保持开关。第三保持开关耦合到至少一个反馈支路，并且M位转换器对耦合到放大器的输出端和第三保持开关。

6. 发明申请

US20110012764A1 MULTIBIT RECYCLIC PIPELINED ADC ARCHITECTURE 有权
标题翻译：多重循环管道ADC架构
公开(公告)号：US20110012764A1
公开(公告)日：2011-01-20
申请号：US12639705
申请日：2009-12-16
申请人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
发明人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/0695 , H03M1/167
摘要： An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
摘要翻译：提供了一种装置。该装置包括采样开关，采样电容器，放大器，反馈分支，第二保持开关，N位转换器对，第三保持开关和M位转换器对。样本接收输入信号并由样本信号启动。采样电容器耦合到采样开关。放大器具有耦合到采样电容器的第一输入端。反馈支路耦合在放大器的输出端和放大器的第一输入端之间，每个反馈支路包括反馈电容器，以及耦合到反馈电容器的第一保持开关。第二保持开关耦合到采样开关。 N位转换器对耦合到采样开关和第二保持开关。第三保持开关耦合到至少一个反馈支路，并且M位转换器对耦合到放大器的输出端和第三保持开关。

7. 发明授权

US07595744B2 Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters 有权
标题翻译：纠正与流水线模数转换器中的子ADC相关的偏移误差
公开(公告)号：US07595744B2
公开(公告)日：2009-09-29
申请号：US11945278
申请日：2007-11-27
申请人： Nitin Agarwal , Ramesh Kumar Singh , Visvesvaraya A Pentakota , Dantes John , Supreet Joshi
发明人： Nitin Agarwal , Ramesh Kumar Singh , Visvesvaraya A Pentakota , Dantes John , Supreet Joshi
IPC分类号： H03M1/10
CPC分类号： H03M1/1023 , H03M1/0607 , H03M1/0624 , H03M1/167 , H03M1/362
摘要： An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
摘要翻译：偏移校正电路检查管线模数转换器（ADC）的级的残留信号，以确定是否需要调整可能导致偏移误差的参数。在一个实施例中，调整参数直到残差信号的最大范围等于预期范围。在所描述的示例中，经调整的参数包括定时偏移误差（当ADC的分量对不同时间的输入信号进行采样时）和电压偏移误差（在产生子码的阶段中的子ADC的阈值电压更改为下一个值）。

8. 发明授权

US07088273B1 Reducing noise in switched capacitor amplifier circuit 有权
标题翻译：降低开关电容放大器电路中的噪声
公开(公告)号：US07088273B1
公开(公告)日：2006-08-08
申请号：US11160855
申请日：2005-07-13
申请人： Sandeep Mallya Perdoor , Visvesvaraya A. Pentakota , Ravishankar S. Ayyagari
发明人： Sandeep Mallya Perdoor , Visvesvaraya A. Pentakota , Ravishankar S. Ayyagari
IPC分类号： H03M1/10
CPC分类号： H03M1/0863 , H03M1/167
摘要： A switched capacitor environment in which a feedback capacitor of a stage is flipped to be used as a sampling capacitor of the next stage. Due to such use of the feedback capacitor, the noise introduced by the stages is substantially reduced. Such switched capacitors can be used in analog to digital converters (ADC).
摘要翻译：一种开关电容器环境，其中翻转级的反馈电容器以用作下一级的采样电容器。由于反馈电容器的使用，这些级引入的噪声显着降低。这种开关电容器可用于模数转换器（ADC）。

9. 发明授权

US06977547B2 Minimizing changes in the amplification factor of an amplification circuit during operation 有权
标题翻译：最大限度地减少放大电路在放大电路中的变化
公开(公告)号：US06977547B2
公开(公告)日：2005-12-20
申请号：US10722409
申请日：2003-11-28
申请人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota
发明人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota
IPC分类号： H03F3/45
CPC分类号： H03F3/45977
摘要： A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification factor of an amplification circuit during operation.
摘要翻译：在放大器的输出端提供电阻器（或具有不改变的阻抗的部件），这使得放大电路在操作期间的放大系数的变化最小化。

10. 发明授权

US06847321B1 Closed loop amplification with high throughput performance 有权
标题翻译：具有高吞吐量性能的闭环放大
公开(公告)号：US06847321B1
公开(公告)日：2005-01-25
申请号：US10706030
申请日：2003-11-13
申请人： Visvesvaraya A. Pentakota , Sandeep K. Oswal
发明人： Visvesvaraya A. Pentakota , Sandeep K. Oswal
IPC分类号： H03F1/34 , H03M1/06 , H03M1/10 , H03M1/12
CPC分类号： H03M1/0604
摘要： Using an operational amplifier with a low gain in a closed loop amplifier circuit, and correcting for errors (i.e., deviation from the output of an ideal closed loop amplifier using an operational amplifier with infinite gain) that would result from the use of the operational amplifier with low gain. In an embodiment implemented in relation to an analog to digital converter (ADC), a mathematical operation is performed on the digital code(s) generated by the ADC to generate a corrected code corresponding to an analog sample.
摘要翻译：在闭环放大器电路中使用具有低增益的运算放大器，并且通过使用运算放大器来校正误差（即，使用具有无限增益的运算放大器的理想闭环放大器的输出的偏差）低增益。在关于模数转换器（ADC）实现的实施例中，对由ADC生成的数字代码执行数学运算，以产生对应于模拟采样的校正代码。

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