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1. 发明授权

US08154020B2 Photo-voltaic cell device and display panel 有权
标题翻译：光伏电池装置和显示面板
公开(公告)号：US08154020B2
公开(公告)日：2012-04-10
申请号：US12464118
申请日：2009-05-12
申请人： An-Thung Cho , Chia-Tien Peng , Yu-Cheng Chen , Hong-Zhang Lin , Yi-Chien Wen , Wei-Min Sun , Chi-Mao Hung , Chun-Hsiun Chen
发明人： An-Thung Cho , Chia-Tien Peng , Yu-Cheng Chen , Hong-Zhang Lin , Yi-Chien Wen , Wei-Min Sun , Chi-Mao Hung , Chun-Hsiun Chen
IPC分类号： H01L29/786
CPC分类号： H01L31/075 , H01L31/032 , H01L31/0384 , Y02E10/548
摘要： A photo-voltaic cell device includes a first electrode, an N-type doped silicon-rich dielectric layer, a P-type doped silicon-rich dielectric layer, and a second electrode. The N-type doped silicon-rich dielectric layer is disposed on the first electrode, and the N-type doped silicon-rich dielectric layer is doped with an N-type dopant. The P-type doped silicon-rich dielectric layer is disposed on the N-type doped silicon-rich dielectric layer, and the P-type doped silicon-rich dielectric layer is doped with a P-type dopant. The second electrode is disposed on the P-type doped silicon-rich dielectric layer. A display panel including the photo-voltaic cell device is also provided.
摘要翻译：光伏电池器件包括第一电极，N型掺杂的富硅介电层，P型掺杂的富硅介电层和第二电极。 N型掺杂富硅介电层设置在第一电极上，并且N型掺杂富硅介电层掺杂有N型掺杂剂。 P型掺杂富硅介电层设置在N型掺杂富硅介电层上，P型掺杂富硅介电层掺杂有P型掺杂剂。第二电极设置在P型掺杂的富硅介电层上。还提供了包括光伏电池装置的显示面板。

2. 发明申请

US20100163873A1 PHOTO-VOLTAIC CELL DEVICE AND DISPLAY PANEL 有权
标题翻译：照相电池装置和显示面板
公开(公告)号：US20100163873A1
公开(公告)日：2010-07-01
申请号：US12464118
申请日：2009-05-12
申请人： An-Thung Cho , Chia-Tien Peng , Yu-Cheng Chen , Hong-Zhang Lin , Yi-Chien Wen , Wei-Min Sun , Chi-Mao Hung , Chun-Hsiun Chen
发明人： An-Thung Cho , Chia-Tien Peng , Yu-Cheng Chen , Hong-Zhang Lin , Yi-Chien Wen , Wei-Min Sun , Chi-Mao Hung , Chun-Hsiun Chen
IPC分类号： H01L33/00 , H01L31/032 , H01L29/786
CPC分类号： H01L31/075 , H01L31/032 , H01L31/0384 , Y02E10/548
摘要： A photo-voltaic cell device includes a first electrode, an N-type doped silicon-rich dielectric layer, a P-type doped silicon-rich dielectric layer, and a second electrode. The N-type doped silicon-rich dielectric layer is disposed on the first electrode, and the N-type doped silicon-rich dielectric layer is doped with an N-type dopant. The P-type doped silicon-rich dielectric layer is disposed on the N-type doped silicon-rich dielectric layer, and the P-type doped silicon-rich dielectric layer is doped with a P-type dopant. The second electrode is disposed on the P-type doped silicon-rich dielectric layer. A display panel including the photo-voltaic cell device is also provided.
摘要翻译：光伏电池器件包括第一电极，N型掺杂的富硅介电层，P型掺杂的富硅介电层和第二电极。 N型掺杂富硅介电层设置在第一电极上，并且N型掺杂富硅介电层掺杂有N型掺杂剂。 P型掺杂富硅介电层设置在N型掺杂富硅介电层上，P型掺杂富硅介电层掺杂有P型掺杂剂。第二电极设置在P型掺杂的富硅介电层上。还提供了包括光伏电池装置的显示面板。

3. 发明授权

US08541750B2 X-ray detector and fabrication method thereof 有权
标题翻译： X射线检测器及其制造方法
公开(公告)号：US08541750B2
公开(公告)日：2013-09-24
申请号：US12553982
申请日：2009-09-03
申请人： Yu-Cheng Chen , An-Thung Cho , Ching-Sang Chuang , Chia-Tien Peng
发明人： Yu-Cheng Chen , An-Thung Cho , Ching-Sang Chuang , Chia-Tien Peng
IPC分类号： G01T1/20
CPC分类号： H01L31/085
摘要： A structure of X-ray detector includes a Si-rich dielectric material for serving as a photo-sensing layer to increase light sensitivity. The fabrication method of the X-ray detector including the Si-rich dielectric material needs less photolithography-etching processes, so as to reduce the total thickness of thin film layers and decrease process steps and cost.
摘要翻译： X射线检测器的结构包括用作光敏层的富Si介电材料以增加光敏度。包含富Si介电材料的X射线检测器的制造方法需要较少的光刻蚀刻工艺，以减少薄膜层的总厚度并降低工艺步骤和成本。

4. 发明申请

US20100207033A1 X-RAY DETECTOR AND FABRICATION METHOD THEREOF 有权
标题翻译： X射线探测器及其制造方法
公开(公告)号：US20100207033A1
公开(公告)日：2010-08-19
申请号：US12553982
申请日：2009-09-03
申请人： Yu-Cheng Chen , An-Thung Cho , Ching-Sang Chuang , Chia-Tien Peng
发明人： Yu-Cheng Chen , An-Thung Cho , Ching-Sang Chuang , Chia-Tien Peng
IPC分类号： G01T1/20 , H01L21/336 , H01L21/20 , H01L29/786
CPC分类号： H01L31/085
摘要： A structure of X-ray detector includes a Si-rich dielectric material for serving as a photo-sensing layer to increase light sensitivity. The fabrication method of the X-ray detector including the Si-rich dielectric material needs less photolithography-etching processes, so as to reduce the total thickness of thin film layers and decrease process steps and cost.
摘要翻译： X射线检测器的结构包括用作光敏层的富Si介电材料以增加光敏度。包含富Si介电材料的X射线检测器的制造方法需要较少的光刻蚀刻工艺，以减少薄膜层的总厚度并降低工艺步骤和成本。

5. 发明申请

US20120112214A1 ACTIVE DEVICE ARRAY SUBSTRATE 有权
标题翻译：主动设备阵列基板
公开(公告)号：US20120112214A1
公开(公告)日：2012-05-10
申请号：US13353328
申请日：2012-01-19
申请人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
发明人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
IPC分类号： H01L27/15
CPC分类号： H01L27/1288 , H01L27/1214
摘要： An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.
摘要翻译：提供有源器件阵列衬底。首先，提供具有显示区域和感测区域的基板。然后，在基板的显示区域上设置第一图案化导体层。栅极绝缘体设置在基板上。图案化半导体层，第二图案化导体层和图案化感光介电层设置在栅极绝缘体上，其中第二图案化导体层包括源电极，漏电极和下电极，图案化的感光介电层覆盖第二图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。然后在衬底上设置钝化层。之后，在钝化层上设置包括像素电极和上部电极的第三图案化导体层。

6. 发明申请

US20100267177A1 METHOD FOR FABRICATING ACTIVE DEVICE ARRAY SUBSTRATE 有权
标题翻译：用于制作主动装置阵列基板的方法
公开(公告)号：US20100267177A1
公开(公告)日：2010-10-21
申请号：US12559506
申请日：2009-09-15
申请人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
发明人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
IPC分类号： H01L21/28
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.
摘要翻译：提供一种用于制造有源器件阵列衬底的方法。首先，提供具有显示区域和感测区域的基板。然后，在基板的显示区域上形成第一图案化导体层。在基板上形成栅极绝缘体。图案化的半导体层，第二图案化导体层和图案化的光敏介电层形成在栅极绝缘体上，其中第二图案化导体层包括源电极，漏电极和下电极，图案化的感光介电层覆盖第二图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。然后在衬底上形成钝化层。之后，在钝化层上形成包括像素电极和上电极的第三图案化导体层。

7. 发明授权

US08597968B2 Active device array substrate 有权
标题翻译：有源器件阵列衬底
公开(公告)号：US08597968B2
公开(公告)日：2013-12-03
申请号：US13353328
申请日：2012-01-19
申请人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
发明人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214
摘要： An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.
摘要翻译：提供有源器件阵列衬底。首先，提供具有显示区域和感测区域的基板。然后，在基板的显示区域上设置第一图案化导体层。栅极绝缘体设置在基板上。图案化半导体层，第二图案化导体层和图案化感光介电层设置在栅极绝缘体上，其中第二图案化导体层包括源电极，漏电极和下电极，图案化的感光介电层覆盖第二图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。然后在衬底上设置钝化层。之后，在钝化层上设置包括像素电极和上部电极的第三图案化导体层。

8. 发明授权

US08148185B2 Method for fabricating active device array substrate 有权
标题翻译：制造有源器件阵列衬底的方法
公开(公告)号：US08148185B2
公开(公告)日：2012-04-03
申请号：US12559506
申请日：2009-09-15
申请人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
发明人： Yu-Cheng Chen , Chen-Yueh Li , Ching-Sang Chuang , Ching-Chieh Shih , An-Thung Cho
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.
摘要翻译：提供一种用于制造有源器件阵列衬底的方法。首先，提供具有显示区域和感测区域的基板。然后，在基板的显示区域上形成第一图案化导体层。在基板上形成栅极绝缘体。图案化的半导体层，第二图案化导体层和图案化的光敏介电层形成在栅极绝缘体上，其中第二图案化导体层包括源电极，漏电极和下电极，图案化的感光介电层覆盖第二图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。然后在衬底上形成钝化层。之后，在钝化层上形成包括像素电极和上电极的第三图案化导体层。

9. 发明申请

US20120115288A1 METHOD FOR FABRICATING ACTIVE DEVICE ARRAY SUBSTRATE 有权
标题翻译：用于制作主动装置阵列基板的方法
公开(公告)号：US20120115288A1
公开(公告)日：2012-05-10
申请号：US13349586
申请日：2012-01-13
申请人： Ming-Wei Sun , Chen-Yueh Li , Yu-Cheng Chen , Chia-Tien Peng
发明人： Ming-Wei Sun , Chen-Yueh Li , Yu-Cheng Chen , Chia-Tien Peng
IPC分类号： H01L21/336
CPC分类号： H01L27/14692 , H01L27/1214 , H01L27/1288 , H01L27/14609 , H01L27/14623 , H01L27/14645
摘要： A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.
摘要翻译：提供一种用于制造有源器件阵列衬底的方法。第一图案化半导体层，栅极绝缘体，第一图案化导电层和第一介电层依次形成在衬底上。暴露第一图案化半导体层的第一接触孔形成在第一介电层和栅极绝缘体中。第一图案化导电层和设置在其上的第二图案化半导体层同时形成在第一介电层上。第二导电层包括接触导体和底部电极。第二图案化半导体层包括有源层。具有第二接触孔的第二电介质层形成在第一电介质层上，其中一部分第二接触孔露出有源层。通过第二接触孔的一部分电连接到有源层的第三图案化导电层形成在第二介电层上。

10. 发明授权

US08198149B2 Method for fabricating active device array substrate 有权
标题翻译：制造有源器件阵列衬底的方法
公开(公告)号：US08198149B2
公开(公告)日：2012-06-12
申请号：US13349586
申请日：2012-01-13
申请人： Ming-Wei Sun , Chen-Yueh Li , Yu-Cheng Chen , Chia-Tien Peng
发明人： Ming-Wei Sun , Chen-Yueh Li , Yu-Cheng Chen , Chia-Tien Peng
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/14692 , H01L27/1214 , H01L27/1288 , H01L27/14609 , H01L27/14623 , H01L27/14645
摘要： A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.
摘要翻译：提供一种用于制造有源器件阵列衬底的方法。第一图案化半导体层，栅极绝缘体，第一图案化导电层和第一介电层依次形成在衬底上。暴露第一图案化半导体层的第一接触孔形成在第一介电层和栅极绝缘体中。第一图案化导电层和设置在其上的第二图案化半导体层同时形成在第一介电层上。第二导电层包括接触导体和底部电极。第二图案化半导体层包括有源层。具有第二接触孔的第二电介质层形成在第一电介质层上，其中一部分第二接触孔露出有源层。通过第二接触孔的一部分电连接到有源层的第三图案化导电层形成在第二介电层上。

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