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1. 发明申请

US20080096335A1 SiC metal semiconductor field-effect transistors and methods for producing same 失效
标题翻译： SiC金属半导体场效应晶体管及其制造方法
公开(公告)号：US20080096335A1
公开(公告)日：2008-04-24
申请号：US12001806
申请日：2007-12-13
申请人： An-Ping Zhang , Larry Rowland , James Kretchmer , Jesse Tucker , Edmund Kaminsky
发明人： An-Ping Zhang , Larry Rowland , James Kretchmer , Jesse Tucker , Edmund Kaminsky
IPC分类号： H01L21/04
CPC分类号： H01L29/8128 , H01L29/1608
摘要： A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.
摘要翻译：碳化硅金属半导体场效应晶体管包括用于改善沟道区域中的电子限制的双层碳化硅缓冲器和/或设置在晶体管的至少沟道区域上的层，用于抑制由悬挂键和界面引起的表面效应状态。而且，倾斜的MESA制造方法利用在MESA处理期间保护MESA顶表面的电介质蚀刻掩模，并且能够形成倾斜的MESA侧壁。

2. 发明申请

US20060043379A1 SIC metal semiconductor field-effect transistors and methods for producing same 失效
标题翻译： SIC金属半导体场效应晶体管及其制造方法
公开(公告)号：US20060043379A1
公开(公告)日：2006-03-02
申请号：US10930584
申请日：2004-08-31
申请人： An-Ping Zhang , Larry Rowland , James Kretchmer , Jesse Tucker , Edmund Kaminsky
发明人： An-Ping Zhang , Larry Rowland , James Kretchmer , Jesse Tucker , Edmund Kaminsky
IPC分类号： H01L21/338 , H01L29/80
CPC分类号： H01L29/8128 , H01L29/1608
摘要： A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.
摘要翻译：碳化硅金属半导体场效应晶体管包括用于改善沟道区域中的电子限制的双层碳化硅缓冲器和/或设置在晶体管的至少沟道区域上的层，用于抑制由悬挂键和界面引起的表面效应状态。而且，倾斜的MESA制造方法利用在MESA处理期间保护MESA顶表面的电介质蚀刻掩模，并且能够形成倾斜的MESA侧壁。

3. 发明申请

US20080124851A1 GaN-based high electron mobility transistor and method for making the same 失效
标题翻译： GaN系高电子迁移率晶体管及其制造方法
公开(公告)号：US20080124851A1
公开(公告)日：2008-05-29
申请号：US11980270
申请日：2007-10-30
申请人： An-Ping Zhang , James Kretchmer , Edmund Kaminsky
发明人： An-Ping Zhang , James Kretchmer , Edmund Kaminsky
IPC分类号： H01L21/338
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462 , H01L29/7783
摘要： A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.
摘要翻译：一种高电子迁移率晶体管，包括：基于GaN材料体系的异质结构; 在异质结构上方钝化氮化物层并限定多个开口; 以及用于异质结构并通过开口形成的多个电触点。

4. 发明申请

US20060226442A1 GaN-based high electron mobility transistor and method for making the same 审中-公开
标题翻译： GaN系高电子迁移率晶体管及其制造方法
公开(公告)号：US20060226442A1
公开(公告)日：2006-10-12
申请号：US11100672
申请日：2005-04-07
申请人： An-Ping Zhang , James Kretchmer , Edmund Kaminsky
发明人： An-Ping Zhang , James Kretchmer , Edmund Kaminsky
IPC分类号： H01L31/00
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462 , H01L29/7783
摘要： A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.
摘要翻译：一种高电子迁移率晶体管，包括：基于GaN材料体系的异质结构; 在异质结构上方钝化氮化物层并限定多个开口; 以及用于异质结构并通过开口形成的多个电触点。

5. 发明授权

US07851284B2 Method for making GaN-based high electron mobility transistor 失效
标题翻译：制造GaN基高电子迁移率晶体管的方法
公开(公告)号：US07851284B2
公开(公告)日：2010-12-14
申请号：US11980270
申请日：2007-10-30
申请人： An-Ping Zhang , James Kretchmer , Edmund Kaminsky, Jr.
发明人： An-Ping Zhang , James Kretchmer , Edmund Kaminsky, Jr.
IPC分类号： H01L21/338
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462 , H01L29/7783
摘要： A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.
摘要翻译：一种高电子迁移率晶体管，包括：基于GaN材料体系的异质结构; 在异质结构上方钝化氮化物层并限定多个开口; 以及用于异质结构并通过开口形成的多个电触点。

6. 发明申请

US20050098844A1 Detection system including avalanche photodiode for use in harsh environments 失效
标题翻译：检测系统包括用于恶劣环境的雪崩光电二极管
公开(公告)号：US20050098844A1
公开(公告)日：2005-05-12
申请号：US10994980
申请日：2004-11-19
申请人： Peter Sandvik , Dale Brown , Stephen Arthur , Kevin Matocha , James Kretchmer
发明人： Peter Sandvik , Dale Brown , Stephen Arthur , Kevin Matocha , James Kretchmer
IPC分类号： G01J1/02 , H01J20060101 , H01L31/0232 , H01L31/0248 , H01L31/0304 , H01L31/0312 , H01L31/0352 , H01L31/06 , H01L31/062 , H01L31/107 , H01L31/113 , H01L31/115
CPC分类号： H01L31/02322 , H01L31/02161 , H01L31/03044 , H01L31/0312 , H01L31/035281 , H01L31/107 , H01L31/115
摘要： An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150° C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials. According to an embodiment of the present invention, an avalanche photodiode for detecting ultraviolet photons comprises a substrate having a first dopant; a first layer having the first dopant, positioned on top of the substrate; a second layer having a second dopant, positioned on top of the first layer; a third layer having a second dopant, positioned on top of the second layer; a passivation layer for providing electrical passivation on a surface of the avalanche photodiode; a phosphorous silicate glass layer for limiting mobile ion transport, positioned on top of the third layer; and a pair of metal electrodes for providing an ohmic contact wherein a first electrode is positioned below the substrate and a second electrode is positioned above the third layer; wherein the avalanche photodiode comprises a first sidewall and a second sidewall forming a sloped mesa shape; and wherein the avalanche photodiode operates in an environment comprising a temperature approximately equal to 150 degrees Celsius.
摘要翻译：本发明的一个方面涉及一种雪崩光电二极管（APD）装置，用于在冲击水平接近250重力加速度（G）和/或温度接近或超过150°的恶劣的井下环境中的油井钻井应用 C.本发明的另一方面涉及使用SiC材料制造的APD器件。本发明的另一方面涉及使用GaN材料制造的APD器件。根据本发明的实施例，用于检测紫外光子的雪崩光电二极管包括具有第一掺杂剂的衬底; 具有第一掺杂剂的第一层，位于衬底的顶部; 具有位于所述第一层的顶部上的具有第二掺杂剂的第二层; 具有第二掺杂剂的第三层，位于所述第二层的顶部; 用于在雪崩光电二极管的表面上提供电钝化的钝化层; 用于限制移动离子迁移的磷硅酸盐玻璃层，位于第三层的顶部; 以及用于提供欧姆接触的一对金属电极，其中第一电极位于所述衬底下方，并且第二电极位于所述第三层之上; 其中所述雪崩光电二极管包括形成倾斜台面形状的第一侧壁和第二侧壁; 并且其中所述雪崩光电二极管在包括大约等于150摄氏度的温度的环境中操作。

7. 发明申请

US20050101100A1 Integrated devices with optical and electrical isolation and method for making 有权
标题翻译：具有光学和电气隔离的集成器件和制造方法
公开(公告)号：US20050101100A1
公开(公告)日：2005-05-12
申请号：US10701534
申请日：2003-11-06
申请人： James Kretchmer , Jeffrey Fedison , Dale Brown , Peter Sandvik
发明人： James Kretchmer , Jeffrey Fedison , Dale Brown , Peter Sandvik
IPC分类号： H01L21/762 , H01L21/763 , H01L27/146 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76224 , H01L27/1463 , H01L27/14643
摘要： The invention is directed to a method for optical and electrical isolation between adjacent integrated devices. The method comprises the steps of forming at least one trench through an exposed surface of a semiconductor wafer by removing a portion of the semiconductor wafer material, forming an electrically insulating layer on the sidewalls and the bottom of the at least one trench, filling the at least one trench by conformally depositing an optically isolating material, and planarizing the semiconductor wafer surface by removing the portion of the optically isolating material above the exposed surface of the semiconductor wafer.
摘要翻译：本发明涉及一种用于在相邻集成器件之间进行光学和电气隔离的方法。该方法包括以下步骤：通过去除半导体晶片材料的一部分，在半导体晶片的暴露表面上形成至少一个沟槽，在至少一个沟槽的侧壁和底部上形成电绝缘层，通过共形沉积光学隔离材料的至少一个沟槽，以及通过去除半导体晶片的暴露表面上方的光学隔离材料的部分来平坦化半导体晶片表面。

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