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1. 发明授权

US09292651B2 System for partitioning integrated circuit design based on timing slack 有权
标题翻译：基于定时松弛的集成电路设计分区系统
公开(公告)号：US09292651B2
公开(公告)日：2016-03-22
申请号：US14195827
申请日：2014-03-03
申请人： Chetan Verma , Amit Kumar Dey , Ashis Maitra , Kulbhushan Misri , Amit Roy , Harkaran Singh , Vijay Tayal
发明人： Chetan Verma , Amit Kumar Dey , Ashis Maitra , Kulbhushan Misri , Amit Roy , Harkaran Singh , Vijay Tayal
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/84
摘要： A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.
摘要翻译：使用EDA工具的IC的物理设计方法包括识别具有过多正时序松弛的IC设计的元件。过多的定时松弛元件被放置在单独的分区中，然后修改多余的定时松弛元件的特性的参数以减少它们的超时间松弛，例如降低提供给单独隔板的电压，从而降低IC的功耗设计。

2. 发明授权

US08803591B1 MOS transistor with forward bulk-biasing circuit 有权
标题翻译： MOS晶体管具有正向体积偏置电路
公开(公告)号：US08803591B1
公开(公告)日：2014-08-12
申请号：US14072809
申请日：2013-11-06
申请人： Amit Roy , Amit Kumar Dey , Kulbhushan Misri , Vijay Tayal , Chetan Verma
发明人： Amit Roy , Amit Kumar Dey , Kulbhushan Misri , Vijay Tayal , Chetan Verma
IPC分类号： H03K3/01 , G05F5/00 , H03K19/00 , G05F3/20
CPC分类号： G05F5/00 , G05F3/205 , H03K19/0027
摘要： Forward bulk biasing circuitry for PMOS and NMOS transistors is provided. The bulk biasing circuitry includes two N-type MOS transistors, two P-type MOS transistors, and two capacitors. The forward bias to a bulk terminal of a transistor increases a threshold voltage of a transistor, thereby reducing a transition time and improving the performance of the transistor. The forward bias is provided only when the transistor transitions from one state to another, thereby reducing leakage power dissipation during active and standby modes of an integrated circuit that includes the transistor.
摘要翻译：提供了用于PMOS和NMOS晶体管的正向体偏置电路。体偏置电路包括两个N型MOS晶体管，两个P型MOS晶体管和两个电容器。对晶体管的体积端子的正向偏压增加了晶体管的阈值电压，从而减小了转换时间并提高了晶体管的性能。仅当晶体管从一种状态转变到另一种状态时，才提供正向偏压，从而在包括晶体管的集成电路的有源和待机模式期间减少漏电功率损耗。

3. 发明授权

US09176522B1 Dual-edge gated clock signal generator 有权
标题翻译：双边门控时钟信号发生器
公开(公告)号：US09176522B1
公开(公告)日：2015-11-03
申请号：US14267933
申请日：2014-05-02
申请人： Amit Kumar Dey , Himanshu Mangal , Kulbhushan Misri , Amit Roy , Vijay Tayal , Chetan Verma
发明人： Amit Kumar Dey , Himanshu Mangal , Kulbhushan Misri , Amit Roy , Vijay Tayal , Chetan Verma
IPC分类号： G06F1/04 , H03K3/00 , H03K19/20
CPC分类号： G06F1/04 , H03K19/096 , H03K19/20
摘要： A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.
摘要翻译：时钟信号发生器提供门控时钟信号GCLK以触发双边缘触发电路的操作。当时钟门控信号/ EN被断言时，第一检测器产生一个第一检测器输出信号，该第一检测器输出信号被断言或取消断言作为分离或分别与输入时钟信号CLK和门控时钟信号GCLK 当时钟门控信号/ EN转换。当门控时钟信号/ EN被取消置位时，第二个检测器产生门控时钟信号GCLK的值，作为第一检测器输出信号的函数的值CLK或其补码/ CLK。当时钟选通信号/ EN被断言时，第二个检测器保持门控时钟信号GCLK当时钟门控信号/ EN从解除断言转变为有效时所具有的值。

4. 发明申请

US20150248519A1 SYSTEM FOR PARTITIONING INTEGRATED CIRCUIT DESIGN BASED ON TIMING SLACK 有权
标题翻译：基于时序分块的集成电路设计分区系统
公开(公告)号：US20150248519A1
公开(公告)日：2015-09-03
申请号：US14195827
申请日：2014-03-03
申请人： Chetan Verma , Amit Kumar Dey , Ashis Maitra , Kulbhushan Misri , Amit Roy , Harkaran Singh , Vijay Tayal
发明人： Chetan Verma , Amit Kumar Dey , Ashis Maitra , Kulbhushan Misri , Amit Roy , Harkaran Singh , Vijay Tayal
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/84
摘要： A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.
摘要翻译：使用EDA工具的IC的物理设计方法包括识别具有过多正时序松弛的IC设计的元件。过多的定时松弛元件被放置在单独的分区中，然后修改多余的定时松弛元件的特性的参数以减少它们的过多的定时松弛，例如降低提供给单独隔板的电压，从而降低IC的功耗设计。

5. 发明申请

US20150316950A1 DUAL-EDGE GATED CLOCK SIGNAL GENERATOR 有权
标题翻译：双边门控时钟信号发生器
公开(公告)号：US20150316950A1
公开(公告)日：2015-11-05
申请号：US14267933
申请日：2014-05-02
申请人： Amit Kumar Dey , Himanshu Mangal , Kulbhushan Misri , Amit Roy , Vijay Tayal , Chetan Verma
发明人： Amit Kumar Dey , Himanshu Mangal , Kulbhushan Misri , Amit Roy , Vijay Tayal , Chetan Verma
IPC分类号： G06F1/04 , H03K19/20
CPC分类号： G06F1/04 , H03K19/096 , H03K19/20
摘要： A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.
摘要翻译：时钟信号发生器提供门控时钟信号GCLK以触发双边缘触发电路的操作。当时钟门控信号/ EN被断言时，第一检测器产生一个第一检测器输出信号，该第一检测器输出信号被断言或取消断言作为分离或分别与输入时钟信号CLK和门控时钟信号GCLK 当时钟门控信号/ EN转换。当门控时钟信号/ EN被取消置位时，第二个检测器产生门控时钟信号GCLK的值，作为第一检测器输出信号的函数的值CLK或其补码/ CLK。当时钟选通信号/ EN被断言时，第二个检测器保持门控时钟信号GCLK当时钟门控信号/ EN从解除断言转变为有效时所具有的值。

6. 发明授权

US08887120B1 Timing path slack monitoring system 有权
标题翻译：定时路径松弛监控系统
公开(公告)号：US08887120B1
公开(公告)日：2014-11-11
申请号：US14141473
申请日：2013-12-27
申请人： Chetan Verma , Amit Kumar Dey , Amit Roy , Vijay Tayal
发明人： Chetan Verma , Amit Kumar Dey , Amit Roy , Vijay Tayal
IPC分类号： G06F17/50 , G06F19/00 , G01R13/00 , G01R29/00 , G01R23/00 , H01L25/00 , H03K19/00
CPC分类号： G06F17/5031 , G01R13/00 , G01R23/00 , G01R29/00 , G06F19/00 , G06F2217/14 , G06F2217/70 , G06F2217/84 , H01L25/00 , H01L2924/0002 , H03K5/04 , H03K5/06 , H03K19/00 , H01L2924/00
摘要： An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.
摘要翻译：测量关键路径末端的定时松弛的片上定时松弛监视器包括具有在主机的Q输出上的抽头的主从触发器和耦合到触发器的逻辑模块，用于产生脉冲其宽度是松弛的函数。脉冲宽度收缩延迟线消除触发器输出上的毛刺，并且与数字积分器和计数器组合，还执行时间到数字转换操作，以确定定时路径松弛的值。确定的值由决策模块用于收益率分析。监视器可以将触发器输出上的毛刺脉冲与任何一个时钟周期的任何一个毛刺宽度区分开来。

7. 发明申请

US20150102839A1 LOW POWER INVERTER CIRCUIT 有权
标题翻译：低功率逆变器电路
公开(公告)号：US20150102839A1
公开(公告)日：2015-04-16
申请号：US14463673
申请日：2014-08-20
申请人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
发明人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
IPC分类号： H03K19/00 , H03K19/20 , H03K19/017
CPC分类号： H03K19/0013 , H03K19/0016 , H03K19/003 , H03K19/017 , H03K19/01707 , H03K19/20
摘要： A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
摘要翻译：低功率逆变器电路包括在其栅极端子处接收输入信号的第一和第二晶体管。第一和第二晶体管分别通过其源极端子连接到第三和第四晶体管。第三和第四晶体管分别与第五和第六晶体管并联连接。第三和第四晶体管被连续接通，并且当输入信号从一个状态转变到另一个状态时，第五和第六晶体管以这样的方式被控制，以减少流过第一和第二晶体管的短路电流。

8. 发明授权

US09166585B2 Low power inverter circuit 有权
标题翻译：低功率逆变电路
公开(公告)号：US09166585B2
公开(公告)日：2015-10-20
申请号：US14463673
申请日：2014-08-20
申请人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
发明人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
IPC分类号： H03K19/003 , H03K19/00 , H03K19/017 , H03K19/20
CPC分类号： H03K19/0013 , H03K19/0016 , H03K19/003 , H03K19/017 , H03K19/01707 , H03K19/20
摘要： A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
摘要翻译：低功率逆变器电路包括在其栅极端子处接收输入信号的第一和第二晶体管。第一和第二晶体管分别通过其源极端子连接到第三和第四晶体管。第三和第四晶体管分别与第五和第六晶体管并联连接。第三和第四晶体管被连续接通，并且当输入信号从一个状态转变到另一个状态时，第五和第六晶体管以这样的方式被控制，以减少流过第一和第二晶体管的短路电流。

9. 发明授权

US09003351B1 System and method for reducing power consumption of integrated circuit 有权
标题翻译：降低集成电路功耗的系统和方法
公开(公告)号：US09003351B1
公开(公告)日：2015-04-07
申请号：US14150731
申请日：2014-01-08
申请人： Chetan Verma , Kushagra Khorwal , Amit Roy , Rounak Roy , Vijay Tayal
发明人： Chetan Verma , Kushagra Khorwal , Amit Roy , Rounak Roy , Vijay Tayal
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/78
摘要： A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.
摘要翻译：一种通过分析和修改跨越多个金属层具有多个网络的布局设计来减少具有EDA工具的集成电路的功耗的方法和系统。该方法包括在布局设计中识别长网，确定每个长网的互连电容，确定每个长网的净电平切换活动，使用互连电容产生高功率冲击列表，以及切换活动每个长网，修改高功率影响列表中列出的长网的金属间距。

10. 发明授权

US08762922B1 System for reducing leakage power of electronic circuit 有权
标题翻译：减少电子电路泄漏功率的系统
公开(公告)号：US08762922B1
公开(公告)日：2014-06-24
申请号：US14052764
申请日：2013-10-13
申请人： Amit Roy , Vijay Tayal , Chetan Verma
发明人： Amit Roy , Vijay Tayal , Chetan Verma
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A system for reducing leakage power of an electronic circuit design, where the circuit design includes multiple timing paths, each timing path made up of multiple cells, using an electronic design automation (EDA) tool. The EDA tool includes a processor that chooses a first replacement cell for replacing a first cell in a first timing path when timing slack is not available in the first path, where a width and threshold voltage of the first replacement cell are greater than a width and threshold voltage of the first cell. The processor then replaces the first cell with the first replacement cell when the overall power consumption of the first replacement cell is less than that of the first cell, and when the timing slack is available for replacing the first cell with the first replacement cell.
摘要翻译：一种用于减少电子电路设计的泄漏功率的系统，其中电路设计包括多个定时路径，使用电子设计自动化（EDA）工具由多个单元构成的每个定时路径。 EDA工具包括一个处理器，当第一路径中的定时松弛不可用时，第一替换单元的宽度和阈值电压大于宽度，选择第一替换单元以替代第一定时路径中的第一单元，并且第一个单元的阈值电压。当第一替换单元的总功耗小于第一单元的整体功率消耗时，以及当定时松弛可用于用第一替换单元替换第一单元时，处理器然后用第一替换单元替换第一单元。

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