会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Quantifying and predicting the impact of line edge roughness on device reliability and performance
    • 量化和预测线边缘粗糙度对器件可靠性和性能的影响
    • US07379924B1
    • 2008-05-27
    • US11001151
    • 2004-12-01
    • Amit P. MaratheCalvin T. Gabriel
    • Amit P. MaratheCalvin T. Gabriel
    • G06F15/18G05B13/00
    • H01L22/20
    • Systems and methods are disclosed for testing semiconductors at the wafer level, specifically, systems and methods are disclosed that quantify line-edge roughness in terms of electrical properties and the impact of the line-edge roughness on device reliability and performance. A voltage ramp dielectric breakdown (VRDB) test is used to measure the breakdown voltage of the inter-digitated fingers of a semiconductor device. The distribution of breakdown voltage is used to measure the median breakdown voltage and the outliers which fan the extrinsic tail. Thereby, VRDB is used to quantify the impact LER will have on device reliability and performance. The systems and methods also provide a feedback tool to the fabrication process to control line edge roughness to a desired specification.
    • 公开了用于在晶片级测试半导体的系统和方法,具体地,公开了在电特性方面量化线边缘粗糙度以及线边缘粗糙度对器件可靠性和性能的影响的系统和方法。 使用电压斜坡绝缘击穿(VRDB)测试来测量半导体器件的数字间指状物的击穿电压。 击穿电压的分布用于测量中间击穿电压和外来尾部的异常值。 因此,VRDB用于量化LER对器件可靠性和性能的影响。 这些系统和方法还为制造过程提供反馈工具,以将线边缘粗糙度控制到期望的规格。
    • 4. 发明授权
    • Tungsten plugs for integrated circuits and methods for making same
    • 用于集成电路的钨插头及其制造方法
    • US5990561A
    • 1999-11-23
    • US97318
    • 1998-06-12
    • Calvin T. GabrielDipankar PramanikXi-Wei Lin
    • Calvin T. GabrielDipankar PramanikXi-Wei Lin
    • H01L21/768H01L23/522H01L23/532H01L23/48H01L23/52
    • H01L21/76843H01L21/76877H01L23/5226H01L23/53257H01L2924/0002
    • A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.
    • 根据本发明的使用钨丝塞的集成电路胶层的制造方法包括:(A)提供具有表面,中心,边缘和与该表面垂直的方向的基板; 和(B)在衬底的表面上溅射沉积胶层,使得在垂直于衬底边缘表面的方向上测量的胶层的边缘厚度为胶的中心厚度的至少105% 层在垂直于衬底中心表面的方向上测量。 在一些实施例中,在垂直于衬底边缘处的表面的方向上测量的所述胶层的边缘厚度在胶层的中心厚度的约105%至150%的范围内,其测量方向是垂直于 在基板的中心处的表面,例如在垂直于基板中心的表面的方向上测量的胶层的中心厚度的约110%至120%的范围内。
    • 6. 发明授权
    • Sloped silicon nitride etch for smoother field oxide edge
    • 用于平滑的场氧化物边缘的斜面氮化硅蚀刻
    • US5702978A
    • 1997-12-30
    • US640092
    • 1996-04-30
    • Calvin T. GabrielOlivier F. Laparra
    • Calvin T. GabrielOlivier F. Laparra
    • H01L21/32H01L21/76
    • H01L21/32
    • A method of fabricating an integrated circuit on a silicon substrate in such a manner as to avoid the requirement of over-etching the polysilicon usually necessary to prevent shorting of adjacent devices by poly filaments caused by deep polysilicon pockets in notch areas created in the field oxide during its growth. The notches are prevented by forming the nitride mask with sloped rather than perpendicular side walls. The sloped side walls present less resistance to the growing oxide than does the usual perpendicular wall and thus does not dig into the growing oxide to form the notches. The edge of the resultant field oxide is therefore smoother, permitting easier and more complete removal of the polysilicon without the need for over-etching.
    • 一种在硅衬底上制造集成电路的方法,以避免过度蚀刻通常必需的多晶硅的需要,以防止由在场氧化物中产生的缺口区域中的深多晶硅袋引起的由多晶丝短路的多晶丝 在它的成长期间。 通过用倾斜而不是垂直的侧壁形成氮化物掩模来防止缺口。 倾斜的侧壁比通常的垂直壁对生长的氧化物具有较小的抵抗力,因此不会进入生长的氧化物以形成凹口。 因此,所得到的场氧化物的边缘更平滑,允许更容易且更完全地去除多晶硅,而不需要过度蚀刻。
    • 7. 发明授权
    • Dummy underlayers for improvement in removal rate consistency during
chemical mechanical polishing
    • 用于改善化学机械抛光过程中去除率一致性的虚拟底层
    • US5639697A
    • 1997-06-17
    • US593900
    • 1996-01-30
    • Milind G. WelingSubhas BothraCalvin T. Gabriel
    • Milind G. WelingSubhas BothraCalvin T. Gabriel
    • H01L21/3105H01L21/302H01L21/463
    • H01L21/31053Y10S438/926
    • A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.
    • 公开了用于不同层的半导体晶片的形貌图案密度的方法,以改进在晶片处理期间使用的化学机械抛光工艺。 为了实现晶片表面上的预定图案形状密度,根据需要将虚拟凸起线插入到迹线层上的有源导电迹线之间的间隙中。 在一些实施例中,预定图案密度在大约40%至80%的范围内。 在一些应用中,活性导电迹线和虚拟凸起线都由金属材料形成,该金属材料在化学机械抛光过程之前在一个步骤中沉积,绝缘层沉积在两个有源导电迹线和虚拟凸起线上 。 在其他应用中,假凸起线由绝缘层形成。
    • 8. 发明授权
    • Semiconductor processing method for preventing corrosion of metal film
connections
    • 用于防止金属膜连接腐蚀的半导体加工方法
    • US5462892A
    • 1995-10-31
    • US180193
    • 1994-01-11
    • Calvin T. Gabriel
    • Calvin T. Gabriel
    • H01L21/02H01L21/3213H01L21/768H01L21/283H01L21/31
    • H01L21/02071H01L21/76886Y10S148/015
    • A semiconductor wafer is processed so as to inhibit corrosion of aluminum or other metal interconnection lines thereon. The anti-corrosion processing of the wafer takes place after forming a metal layer on a semiconductor wafer, masking the metal layer with resist and reactive ion etching the conductive layer in an evacuated chamber so as to form metal interconnection lines. The semiconductor wafer is then moved under vacuum to a second evacuated chamber, where an oxide is formed on sidewalls of the metal layer by heating the semiconductor wafer while flowing dry oxygen-containing gas. The oxide on the sidewalls of the metal layer prevents corrosion of the metal layer by reactive halogen compounds remaining on the semiconductor wafer after the reactive ion etching step. The resist remaining on the wafer is removed after the semiconductor wafer is removed from the second evacuated chamber. Typically, the metal layer is formed from aluminum or aluminum-copper alloy, or from a successive layers of tungsten/titanium and aluminum-copper. The oxide formation step is preferably performed by heating the wafer to a temperature not exceeding 450.degree. C. while flowing dry oxygen-containing gas, at a pressure or about one atmosphere or less, through the second evacuated chamber.
    • 处理半导体晶片以便抑制其上的铝或其它金属互连线的腐蚀。 在半导体晶片上形成金属层之后,利用抗蚀剂掩蔽金属层并在真空室中对导电层进行反应离子蚀刻,形成金属互连线,进行晶片的防腐处理。 然后将半导体晶片在真空下移动到第二真空室,其中通过在流过干含氧气体的同时加热半导体晶片而在金属层的侧壁上形成氧化物。 在金属层的侧壁上的氧化物防止在反应离子蚀刻步骤之后残留在半导体晶片上的活性卤素化合物对金属层的腐蚀。 在将半导体晶片从第二抽空室移除之后,去除残留在晶片上的抗蚀剂。 通常,金属层由铝或铝 - 铜合金形成,或者由钨/钛和铝 - 铜的连续层形成。 氧化物形成步骤优选通过将晶片加热至不超过450℃的温度,同时通过第二抽真空室在约一个或几个大气压或更低的压力下使干燥含氧气体流动。
    • 9. 发明授权
    • Method for moisture sealing integrated circuits using silicon nitride
spacer protection of oxide passivation edges
    • 使用氮化硅隔离保护氧化物钝化边缘的集成电路的湿气密封方法
    • US5294295A
    • 1994-03-15
    • US786322
    • 1991-10-31
    • Calvin T. Gabriel
    • Calvin T. Gabriel
    • H01L21/314H01L23/31B44C1/22
    • H01L23/3192H01L23/3171H01L2924/0002Y10S148/043Y10S438/958
    • For passivation of an integrated circuit device, a film of silicon dioxide is deposited over the integrated circuit device. A film of silicon nitride is deposited over the film of silicon dioxide. The film of silicon nitride and the film of silicon dioxide are etched using a single passivation mask to expose the bond pads of the integrated circuit device. Spacer regions of silicon nitride are placed over edges of the film of silicon dioxide exposed by the etching. The spacer regions may be placed by depositing a second film of silicon nitride over the film of silicon nitride. This second film of silicon nitride covers the metal bond pads and the exposed edges of the film of silicon dioxide. An anisotropic etchback of the second film of silicon nitride is performed to expose the metal bond pads while leaving spacer regions which cover the edges of the film of silicon dioxide.
    • 对于集成电路器件的钝化,二氧化硅膜沉积在集成电路器件上。 氮化硅膜沉积在二氧化硅膜上。 使用单个钝化掩模蚀刻氮化硅膜和二氧化硅膜以暴露集成电路器件的接合焊盘。 氮化硅的间隔区被放置在通过蚀刻暴露的二氧化硅膜的边缘上。 可以通过在氮化硅膜上沉积第二氮化硅膜来放置间隔区。 该第二氮化硅膜覆盖金属接合焊盘和二氧化硅膜的暴露边缘。 执行第二氮化硅膜的各向异性回蚀以暴露金属接合焊盘,同时留下覆盖二氧化硅膜的边缘的间隔区。
    • 10. 发明授权
    • Method for reducing critical dimension attainable via the use of an organic conforming layer
    • 通过使用有机符合层可以降低临界尺寸的方法
    • US06864184B1
    • 2005-03-08
    • US10772830
    • 2004-02-05
    • Calvin T. Gabriel
    • Calvin T. Gabriel
    • H01L21/033H01L21/308H01L21/311H01L21/768H01L21/302
    • H01L21/3081H01L21/0337H01L21/0338H01L21/3086H01L21/31144H01L21/76816
    • In one embodiment, a semiconductor device processing method, comprising the steps of: (a) using a patterned photoresist to form a structure having at least one edge; (b) prior to removal of the photoresist, forming a conforming layer from an organic compound and patterning the conforming layer to form at least one sidewall spacer which are self-aligned to the at least one edge; (c) performing a processing operation which is at least partially localized by the at least one sidewall spacer; and (d) removing the at least one sidewall spacer and the photoresist, wherein the conforming layer is formed via deposition of at least one organic compound selected from C1 to C8 alkanes C2 to C8 alkenes, C3 to C8 cyclo-alkenes, C4 to C8 cyclo-alkenes, C1 to C8 fluoro-alkanes, C2 to C8 fluoro-alkenes, C3 to C8 cyclofluoro-alkanes, C4 to C8 cyclofluoro-alkenes, or mixtures thereof.
    • 在一个实施例中,一种半导体器件处理方法,包括以下步骤:(a)使用图案化的光致抗蚀剂以形成具有至少一个边缘的结构; (b)在去除光致抗蚀剂之前,从有机化合物形成合适的层,并构图所述适形层以形成至少一个与所述至少一个边缘自对准的侧壁间隔物; (c)执行由所述至少一个侧壁间隔件至少部分定位的处理操作; 和(d)去除所述至少一个侧壁间隔物和所述光致抗蚀剂,其中通过沉积至少一种选自C1至C8烷烃C2至C8烯烃,C3至C8环烯烃,C4至C8的有机化合物形成所述一致层 环烯烃,C1至C8氟代烷烃,C2至C8氟代烯烃,C3至C8环氟烷烃,C4至C8环氟烯烃或其混合物。