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1. 发明授权

US06237132B1 Toggle based application specific core methodology 失效
标题翻译：基于应用的切换核心方法
公开(公告)号：US06237132B1
公开(公告)日：2001-05-22
申请号：US09136126
申请日：1998-08-18
申请人： Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Kenneth Torino , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Kenneth Torino , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022
摘要： According to the present invention, an automated method to tailor an ASIC core to meet the needs of an individual system on a chip design is disclosed. The preferred method starts with a technology-independent hardware description language (HDL) representation of the core des i on. This high-level design is subdivided into functions, or blocks. Blocks which cannot be removed without impacting the integrity of the core design an are ta b y ed with “must-keep” indicators. The execution of all application code that will employ the core is simulated on the high-level model. The simulation process accumulates information about what blocks in the model are used by the application code, and which are unused, information about which blocks are unused is combined with information about what blocks are not removable. The high-level core design is then tailored by deleting blocks in the core design that are both unused and removable. The tailored high-level design is then synthesized to a technology-dependent core design. The synthesis process substitutes gates for the blocks, propagating must-keep tags to all gates substituted for a block tagged with a “must-keep” indicator. The simulation of all application code is repeated on the low-level design, and accumulates information about which gates are unused by the application code. The low-level design is then tailored by deleting Yates in the core that are both unused and removable.
摘要翻译：根据本发明，公开了一种定制ASIC核心以满足单个系统在芯片设计上的需要的自动化方法。首选方法是以技术独立的硬件描述语言（HDL）表示为核心。这个高级设计被细分为功能或块。在不影响核心设计的完整性的情况下无法移除的块将使用“必须保留”指示器。在高级模型上模拟使用核心的所有应用程序代码的执行。模拟过程累积关于应用代码使用模型中哪些模块的信息，以及哪些未使用的，哪些块未被使用的信息与什么块不可移动的信息相结合。然后通过删除核心设计中未使用和可移动的块来定制高级核心设计。然后将量身定制的高级设计合成为依赖于技术的核心设计。合成过程将门代替块，将必须保留标签传播到所有门，替代标有“必须”指示符的块。在低级设计中重复所有应用代码的仿真，并通过应用代码累积关于哪些门未被使用的信息。然后，通过在核心中删除既不使用也可拆卸的Yates来定制低级设计。

2. 发明授权

US06397170B1 Simulation based power optimization 有权
标题翻译：基于模拟功率优化
公开(公告)号：US06397170B1
公开(公告)日：2002-05-28
申请号：US09135825
申请日：1998-08-18
申请人： Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A system and method for designing a low power ASIC using weighted net toggle information. In particular, the system and method includes a simulation system that executes a set of application test suites that is representative of the code that will likely run on the ASIC and weights each of the applications. The weighted net toggle information can then be evaluated and utilized to modify the ASIC design.
摘要翻译：一种使用加权网络切换信息设计低功率ASIC的系统和方法。特别地，该系统和方法包括一个模拟系统，它执行代表可能在ASIC上运行的代码并对每个应用进行加权的一组应用测试套件。然后可以评估和利用加权网络切换信息来修改ASIC设计。

3. 发明授权

US06275968B1 Apparatus and method to reduce node toggling in semiconductor devices 失效
标题翻译：减少半导体器件中的节点切换的装置和方法
公开(公告)号：US06275968B1
公开(公告)日：2001-08-14
申请号：US09129921
申请日：1998-08-06
申请人： Alvar A. Dean , Kenneth J. Goodnow , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F1/32 , G06F1/04 , G06F17/505
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded toggling that commonly occurs in many types of logic circuits. The preferred embodiment reduces unneeded node toggling in a circuit by holding a portion of the device at the previous output until the all the inputs have stabilized to their final value during each clock cycle. This reduces power consumption in the device that would normally occur due to unnecessary node toggling.
摘要翻译：根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。优选实施例减少了通常在许多类型的逻辑电路中发生的不必要的切换。优选实施例通过将设备的一部分保持在先前输出来减少电路中的不需要的节点切换，直到所有输入在每个时钟周期内稳定到其最终值。这减少了由于不必要的节点切换而通常发生的设备中的功耗。

4. 发明授权

US06604174B1 Performance based system and method for dynamic allocation of a unified multiport cache 有权
标题翻译：基于性能的系统和方法，用于动态分配统一的多端口缓存
公开(公告)号：US06604174B1
公开(公告)日：2003-08-05
申请号：US09709872
申请日：2000-11-10
申请人： Alvar A. Dean , Kenneth J. Goodnow , Stephen W. Mahin , Wilbur D. Pricer , Dana J. Thygesen , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Stephen W. Mahin , Wilbur D. Pricer , Dana J. Thygesen , Sebastian T. Ventrone
IPC分类号： G06F1200
CPC分类号： G06F12/0853 , G06F12/0844 , G06F12/0846
摘要： The present invention provides a performance based system and method for dynamic allocation of a unified multiport cache. A multiport cache system is disclosed that allows multiple single-cycle look ups through a multiport tag and multiple single-cycle cache accesses from a multiport cache. Therefore, multiple processes, which could be processors, tasks, or threads can access the cache during any cycle. Moreover, the ways of the cache can be allocated to the different processes and then dynamically reallocated based on performance. Most preferably, a relational cache miss percentage is used to reallocate the ways, but other metrics may also be used.
摘要翻译：本发明提供了一种用于动态分配统一多端口高速缓存的基于性能的系统和方法。公开了一种多端口缓存系统，其允许通过多端口标签的多个单周期查找和来自多端口高速缓存的多个单周期高速缓存访问。因此，可能是处理器，任务或线程的多个进程可以在任何周期内访问高速缓存。此外，缓存的方式可以分配给不同的进程，然后基于性能动态重新分配。最优选地，使用关系高速缓存未命中百分比来重新分配方式，但也可以使用其他度量。

5. 发明授权

US06317840B1 Control of multiple equivalent functional units for power reduction 有权
标题翻译：控制功率降低的多个等效功能单元
公开(公告)号：US06317840B1
公开(公告)日：2001-11-13
申请号：US09275170
申请日：1999-03-24
申请人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Sebastian T. Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F9/3836 , G06F9/3869 , Y02D10/122 , Y02D10/171
摘要： A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.
摘要翻译：具有用于功率降低的多个等效功能单元的处理器，其包括用于控制功能单元的选择的机构。具体地，处理器包括以第一速度执行预定功能的第一电路，以第二速度执行相同的预定功能的第二电路，以及用于选择第一或第二电路以执行功能的控制系统。控制系统还包括用于控制流水线中的处理器指令的执行速率以便补偿第一或第二回路执行预定功能的速度的机构。

6. 发明授权

US06802033B1 Low-power critical error rate communications controller 失效
标题翻译：低功率关键错误率通信控制器
公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译：一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

7. 发明授权

US06985004B2 Wiring optimizations for power 失效
公开(公告)号：US06985004B2
公开(公告)日：2006-01-10
申请号：US09781369
申请日：2001-02-12
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： H03K17/16
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

8. 发明授权

US06711719B2 Method and apparatus for reducing power consumption in VLSI circuit designs 失效
标题翻译：用于降低VLSI电路设计中的功耗的方法和装置
公开(公告)号：US06711719B2
公开(公告)日：2004-03-23
申请号：US09928573
申请日：2001-08-13
申请人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.
摘要翻译：在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离源不需要传播。由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。因此，整体IC功耗降低。

9. 发明授权

US06687883B2 System and method for inserting leakage reduction control in logic circuits 有权
标题翻译：用于在逻辑电路中插入泄漏减少控制的系统和方法
公开(公告)号：US06687883B2
公开(公告)日：2004-02-03
申请号：US09750969
申请日：2000-12-28
申请人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152 , Y02D50/20
摘要： A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.
摘要翻译：一种用于减少逻辑网络的泄漏功率的方法，包括以下步骤：使用（可观察性）不关心信息以识别各个网络的“睡眠状态”; 基于概率分析确定至少一个网络，其中通过在“睡眠状态”的至少一部分期间将网络强制为特定值来减少预期功率消耗; 并将所确定的网络强制为所述“睡眠状态”的确定值确定部分。

10. 发明授权

US07346875B2 Wiring optimizations for power 有权
标题翻译：电力接线优化
公开(公告)号：US07346875B2
公开(公告)日：2008-03-18
申请号：US11176712
申请日：2005-07-07
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.
摘要翻译：电气布线结构及其设计方法。该方法识别具有第一线和第二线的至少一个线对。第二根线已经是三态的，也可以是三态的。线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

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