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1. 发明授权

US06636995B1 Method of automatic latch insertion for testing application specific integrated circuits 失效
标题翻译：用于测试专用集成电路的自动锁存插入方法
公开(公告)号：US06636995B1
公开(公告)日：2003-10-21
申请号：US09615146
申请日：2000-07-13
申请人： Alvar A. Dean , Joseph A. Iadanza , David E. Lackey , Sebastian T. Ventrone
发明人： Alvar A. Dean , Joseph A. Iadanza , David E. Lackey , Sebastian T. Ventrone
IPC分类号： G01R3128
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A method of testing a digital logic circuit comprises first providing a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit. As a result of the method of the present invention, testing is completed in a time faster than if the nets were tested without the control latches and the observation latches. The portion of the nets which are most difficult to test are preferably identified by overall test time impact, and the nets having longest test times are determined to be most difficult to control and most difficult to observe.
摘要翻译：一种测试数字逻辑电路的方法包括：首先提供具有多个互连电路的逻辑电路，每个互连电路具有输入和输出; 确定逻辑电路的门级表示，包括用于确定电路中的故障的测试网; 并且识别最难测试的网的一部分，包括最难控制的网和最难观察的网。该方法然后包括将被确定为最难控制并插入用于被确定为最难观察的网络的逻辑电路观察锁存器的网络的逻辑电路控制锁存器插入。使用插入的控制锁存器和观察锁存器，该方法还包括测试被确定为最难控制的网络，并且网络中难以观察和确定电路中的故障。作为本发明的方法的结果，比没有控制锁存器和观察锁存器测试网络的时间更快地完成测试。最难测试的网的部分优选通过整体测试时间的影响来确定，并且确定具有最长测试时间的网最难以控制并且最难观察。

2. 发明授权

US06487701B1 System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology 失效
标题翻译：通过液晶半导体技术中的阈值电压偏移进行交流性能调谐的系统和方法
公开(公告)号：US06487701B1
公开(公告)日：2002-11-26
申请号：US09711744
申请日：2000-11-13
申请人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
发明人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G01R31/3163 , G01R31/2891
摘要： A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.
摘要翻译：描述了一种系统和方法，用于将半导体晶片上的FET的体连接与电源轨分开，测试晶片以确定晶片内的某些器件的阈值电压VT是否偏移，孔可以去除IC电路中的AC缺陷，并且定制施加到散装节点的电压或电压，后制造，使得集成电路满足其性能目标或被分类到更有价值的性能水平。该方法需要生成IC电路的门级网表，并使用静态时序分析，功能延迟模拟，电路活动分析和功能性能测试来对这些电路网表执行定时计算。然后将故障与相应的IC电路相关联，最坏情况下调查松弛电路，并且在硬件中采用提出的阈值电压的改变。

3. 发明授权

US07932774B2 Structure for intrinsic RC power distribution for noise filtering of analog supplies 有权
标题翻译：用于模拟电源噪声滤波的固有RC功率分配的结构
公开(公告)号：US07932774B2
公开(公告)日：2011-04-26
申请号：US12053958
申请日：2008-03-24
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/56
摘要： A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.
摘要翻译：用于模拟电源噪声滤波的固有RC功率分配的设计结构。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括电压调节器; 耦合到电压调节器的可变电阻器; 以及向可变电阻器提供反馈回路的性能监视和控制电路。

4. 发明授权

US07643591B2 Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design 失效
标题翻译：在设计，合成和物理设计过程中，降噪/减少/减少Di / Dt的转换平衡
公开(公告)号：US07643591B2
公开(公告)日：2010-01-05
申请号：US11460065
申请日：2006-07-26
申请人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
摘要翻译：一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟，输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入，为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

5. 发明申请

US20090261882A1 Skewed Double Differential Pair Circuit for Offset Cancelllation 有权
标题翻译：用于偏移消除的偏斜双差分电路
公开(公告)号：US20090261882A1
公开(公告)日：2009-10-22
申请号：US12494642
申请日：2009-06-30
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden (Clay) Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone , Benjamin T. Voegeli
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden (Clay) Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone , Benjamin T. Voegeli
IPC分类号： H03L5/00
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.
摘要翻译：公开了一种使用双差分输入对系统产生具有偏移消除的差分信号的差分系统。它使用两个有意偏斜的并联差分晶体管对。名义上，差分对在每个方向相反的方向上倾斜，但是具有相等的幅度，使得两个差分对的组合被名义上平衡。然后，使用用于在系统的校准模式中为第一和第二差分输入提供等电位值的选择装置，增加或减少通过每个差分对的电流，直到任何偏移被充分抵消为止，以及用于比较第一和第第二差分输出在校准模式下确定系统的偏移。

6. 发明申请

US20090108869A1 Design Structure for a Flexible Multimode Logic Element For Use In A Configurable Mixed-Logic Signal Distribution Path 失效
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模逻辑元件的设计结构
公开(公告)号：US20090108869A1
公开(公告)日：2009-04-30
申请号：US11931626
申请日：2007-10-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/00
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

7. 发明授权

US07479819B2 Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees 失效
公开(公告)号：US07479819B2
公开(公告)日：2009-01-20
申请号：US11610848
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

8. 发明申请

US20080244479A1 STRUCTURE FOR INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：内部RC功率分配结构用于模拟电源的噪声滤波
公开(公告)号：US20080244479A1
公开(公告)日：2008-10-02
申请号：US12053958
申请日：2008-03-24
申请人： Anthony R. BONACCIO , Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. BONACCIO , Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： G06F17/50
CPC分类号： G05F1/56
摘要： A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.
摘要翻译：用于模拟电源噪声滤波的固有RC功率分配的设计结构。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括电压调节器; 耦合到电压调节器的可变电阻器; 以及向可变电阻器提供反馈回路的性能监视和控制电路。

9. 发明授权

US07429877B2 Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模逻辑元件的设计结构
公开(公告)号：US07429877B2
公开(公告)日：2008-09-30
申请号：US11848470
申请日：2007-08-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，用于示例性多模电路的设计结构可以被配置为以全摆动模式，限定摆动模式，全摆幅至限定摆动转换器模式和限定摆动转换模式中的一种运行，摆动转换器模式。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

10. 发明授权

US07404114B2 System and method for balancing delay of signal communication paths through well voltage adjustment 有权
标题翻译：通过井电压调整来平衡信号通信路径的延迟的系统和方法
公开(公告)号：US07404114B2
公开(公告)日：2008-07-22
申请号：US10906343
申请日：2005-02-15
申请人： Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone
发明人： Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone
IPC分类号： G01R31/28
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

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