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1. 发明申请

US20060107247A1 Memory generation and placement 有权
标题翻译：内存生成和放置
公开(公告)号：US20060107247A1
公开(公告)日：2006-05-18
申请号：US10990589
申请日：2004-11-17
申请人： Alexandre Andreev , Ilya Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
发明人： Alexandre Andreev , Ilya Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.
摘要翻译：存储器生成和放置流程系统，其接收客户存储器设计，并将客户存储器设计放置在可定制的标准化集成电路设计中。存储器生成和放置流程系统包括存储库管理器工具，存储器估计器工具和存储器存储器工具。

2. 发明申请

US20070113212A1 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US20070113212A1
公开(公告)日：2007-05-17
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

3. 发明申请

US20070108961A1 Method and apparatus for tiling memories in integrated circuit layout 失效
标题翻译：用于在集成电路布局中平铺存储器的方法和装置
公开(公告)号：US20070108961A1
公开(公告)日：2007-05-17
申请号：US11280879
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
IPC分类号： G01R1/00
CPC分类号： G06F17/5072
摘要： A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.
摘要翻译：提供了一种处理和装置，用于在布局图案中的一个或多个相应的对象位置中平铺诸如设计存储器的对象。对于每个对象，基于对象的容量和宽度与相应对象位置的容量和宽度中的至少一个的比较递归地执行以下步骤：（1）不执行任何操作; （2）重新配置对象具有不同的容量和/或宽度; 和（3）将对象拆分成两个或多个单独的对象。每个重新配置的对象和每个分离的对象重复递归。

4. 发明授权

US07389484B2 Method and apparatus for tiling memories in integrated circuit layout 失效
标题翻译：用于在集成电路布局中平铺存储器的方法和装置
公开(公告)号：US07389484B2
公开(公告)日：2008-06-17
申请号：US11280879
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.
摘要翻译：提供了一种处理和装置，用于在布局图案中的一个或多个相应的对象位置中平铺诸如设计存储器的对象。对于每个对象，基于对象的容量和宽度与相应对象位置的容量和宽度中的至少一个的比较递归地执行以下步骤：（1）不执行任何操作; （2）重新配置对象具有不同的容量和/或宽度; 和（3）将对象拆分成两个或多个单独的对象。每个重新配置的对象和每个分离的对象重复递归。

5. 发明授权

US08566769B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08566769B2
公开(公告)日：2013-10-22
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

6. 发明申请

US20100023904A1 Method and Apparatus for Generating Memory Models and Timing Database 失效
标题翻译：用于生成内存模型和时序数据库的方法和装置
公开(公告)号：US20100023904A1
公开(公告)日：2010-01-28
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

7. 发明授权

US07200826B2 RRAM memory timing learning tool 有权
标题翻译： RRAM内存计时学习工具
公开(公告)号：US07200826B2
公开(公告)日：2007-04-03
申请号：US11000104
申请日：2004-11-30
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of generating a timing model for a customer memory configuration, by generating a plurality of template memory netlists for a given RRAM design. Timing models for the template memory netlists are produced and stored in a first database. The template memory netlists are stored in a second database. A netlist for the customer memory configuration is generated and compared to the template memory netlists to find a match. When a match is found, one of the timing models that is associated with the matching template memory netlist is used as the timing model for the customer memory configuration. When a match is not found, two of the template memory netlists that bound the customer netlist are found, according to at least one parameter, and the timing model for the customer memory configuration is interpolated based on the two bounding template memory netlists.
摘要翻译：一种通过为给定的RRAM设计生成多个模板存储器网表来为客户存储器配置生成定时模型的方法。生成模板内存网表的时序模型并将其存储在第一个数据库中。模板内存网表存储在第二个数据库中。生成客户内存配置的网表，并与模板内存网表进行比较以查找匹配项。当找到匹配时，将与匹配模板内存网表相关联的时序模型之一用作客户内存配置的时间模型。当没有找到匹配时，根据至少一个参数找到绑定客户网表的两个模板存储器网表，并且基于两个边界模板存储器网表来内插客户存储器配置的定时模型。

8. 发明授权

US08245168B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08245168B2
公开(公告)日：2012-08-14
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

9. 发明申请

US20080295044A1 METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：将设计记忆映射到集成电路布局的方法和装置
公开(公告)号：US20080295044A1
公开(公告)日：2008-11-27
申请号：US12186159
申请日：2008-08-05
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

10. 发明授权

US07424687B2 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US07424687B2
公开(公告)日：2008-09-09
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

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