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1. 发明授权

US08566769B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08566769B2
公开(公告)日：2013-10-22
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

2. 发明授权

US08156391B2 Data controlling in the MBIST chain architecture 失效
标题翻译： MBIST链架构中的数据控制
公开(公告)号：US08156391B2
公开(公告)日：2012-04-10
申请号：US12167305
申请日：2008-07-03
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/14 , G11C29/50
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译：一种包括第一电路和第二电路的存储器环。第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。在测试模式期间，可以将一个或多个数据序列呈现给存储器。第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。

3. 发明申请

US20100023904A1 Method and Apparatus for Generating Memory Models and Timing Database 失效
标题翻译：用于生成内存模型和时序数据库的方法和装置
公开(公告)号：US20100023904A1
公开(公告)日：2010-01-28
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

4. 发明申请

US20090300441A1 ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 有权
标题翻译：地址控制在MBIST链建筑
公开(公告)号：US20090300441A1
公开(公告)日：2009-12-03
申请号：US12183562
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译：存储器环包括第一电路，第二电路和第三电路。第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。第三电路可以被配置为生成一个或多个地址序列。在测试模式期间将一个或多个地址序列呈现给存储器。

5. 发明授权

US07200826B2 RRAM memory timing learning tool 有权
标题翻译： RRAM内存计时学习工具
公开(公告)号：US07200826B2
公开(公告)日：2007-04-03
申请号：US11000104
申请日：2004-11-30
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of generating a timing model for a customer memory configuration, by generating a plurality of template memory netlists for a given RRAM design. Timing models for the template memory netlists are produced and stored in a first database. The template memory netlists are stored in a second database. A netlist for the customer memory configuration is generated and compared to the template memory netlists to find a match. When a match is found, one of the timing models that is associated with the matching template memory netlist is used as the timing model for the customer memory configuration. When a match is not found, two of the template memory netlists that bound the customer netlist are found, according to at least one parameter, and the timing model for the customer memory configuration is interpolated based on the two bounding template memory netlists.
摘要翻译：一种通过为给定的RRAM设计生成多个模板存储器网表来为客户存储器配置生成定时模型的方法。生成模板内存网表的时序模型并将其存储在第一个数据库中。模板内存网表存储在第二个数据库中。生成客户内存配置的网表，并与模板内存网表进行比较以查找匹配项。当找到匹配时，将与匹配模板内存网表相关联的时序模型之一用作客户内存配置的时间模型。当没有找到匹配时，根据至少一个参数找到绑定客户网表的两个模板存储器网表，并且基于两个边界模板存储器网表来内插客户存储器配置的定时模型。

6. 发明申请

US20060129874A1 Master controller architecture 失效
标题翻译：主控制器架构
公开(公告)号：US20060129874A1
公开(公告)日：2006-06-15
申请号：US10999720
申请日：2004-11-30
申请人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
发明人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72
摘要： A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要翻译：用于RRAM子系统的主控制器。接口与至少一个RRAM控制器通信。主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。定时器确定在给定时间内可以实现的最大测试和修复操作数。因此，主控制器包含在RRAM子系统中。主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。以这种方式，RRAM子系统具有自修复功能。

7. 发明申请

US20060107247A1 Memory generation and placement 有权
标题翻译：内存生成和放置
公开(公告)号：US20060107247A1
公开(公告)日：2006-05-18
申请号：US10990589
申请日：2004-11-17
申请人： Alexandre Andreev , Ilya Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
发明人： Alexandre Andreev , Ilya Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.
摘要翻译：存储器生成和放置流程系统，其接收客户存储器设计，并将客户存储器设计放置在可定制的标准化集成电路设计中。存储器生成和放置流程系统包括存储库管理器工具，存储器估计器工具和存储器存储器工具。

8. 发明授权

US07949909B2 Address controlling in the MBIST chain architecture 有权
标题翻译：地址控制在MBIST链架构
公开(公告)号：US07949909B2
公开(公告)日：2011-05-24
申请号：US12183562
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译：存储器环包括第一电路，第二电路和第三电路。第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。第三电路可以被配置为生成一个或多个地址序列。在测试模式期间将一个或多个地址序列呈现给存储器。

9. 发明申请

US20100070548A1 UNIVERSAL GALOIS FIELD MULTIPLIER 有权
标题翻译：通用GALOIS场地乘法器
公开(公告)号：US20100070548A1
公开(公告)日：2010-03-18
申请号：US12211268
申请日：2008-09-16
申请人： Sergei B. Gashkov , Alexandre Andreev
发明人： Sergei B. Gashkov , Alexandre Andreev
IPC分类号： G06F17/10
CPC分类号： G06F7/724
摘要： An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.
摘要翻译：一种包括乘法器电路和复用电路的装置。乘法器电路可以被配置为基于可编程基值乘以第一被乘数和第二被乘数，并且生成多个中间值，每个中间值表示乘法的结果减去相应的不可约多项式。复用电路可以被配置为响应于从乘法器电路接收的多个中间值和可编程基值产生输出。

10. 发明授权

US07389484B2 Method and apparatus for tiling memories in integrated circuit layout 失效
标题翻译：用于在集成电路布局中平铺存储器的方法和装置
公开(公告)号：US07389484B2
公开(公告)日：2008-06-17
申请号：US11280879
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.
摘要翻译：提供了一种处理和装置，用于在布局图案中的一个或多个相应的对象位置中平铺诸如设计存储器的对象。对于每个对象，基于对象的容量和宽度与相应对象位置的容量和宽度中的至少一个的比较递归地执行以下步骤：（1）不执行任何操作; （2）重新配置对象具有不同的容量和/或宽度; 和（3）将对象拆分成两个或多个单独的对象。每个重新配置的对象和每个分离的对象重复递归。

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