专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060285394A1 Method of programming a non-volatile memory cell by controlling the channel current during the rise period 有权
标题翻译：通过在上升期间控制通道电流来对非易失性存储单元进行编程的方法
公开(公告)号：US20060285394A1
公开(公告)日：2006-12-21
申请号：US11487135
申请日：2006-07-14
申请人： Alexander Kotov , Yuniarto Widjaja , Tho Dang , Hung Nguyen , Sang Nguyen
发明人： Alexander Kotov , Yuniarto Widjaja , Tho Dang , Hung Nguyen , Sang Nguyen
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.
摘要翻译：公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。该方法消除或最小化孔位移电流的影响。这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

2. 发明申请

US20050078526A1 Method of programming a non-volatile memory cell to eliminate or to minimize program deceleration 有权
标题翻译：编程非易失性存储单元以消除或最小化程序减速的方法
公开(公告)号：US20050078526A1
公开(公告)日：2005-04-14
申请号：US10944584
申请日：2004-09-16
申请人： Alexander Kotov , Yuniarto Widjaja , Tho Ngoc Dang , Hung Nguyen , Sang Nguyen
发明人： Alexander Kotov , Yuniarto Widjaja , Tho Ngoc Dang , Hung Nguyen , Sang Nguyen
IPC分类号： G11C16/12 , G11C11/34
CPC分类号： G11C16/12
摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.
摘要翻译：公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。该方法消除或最小化孔位移电流的影响。这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

3. 发明申请

US20050201152A1 CIRCUIT AND A METHOD TO SCREEN FOR DEFECTS IN AN ADDRESSABLE LINE IN A NON-VOLATILE MEMORY 有权
标题翻译：电路和非易失性存储器中可寻址线路中缺陷的屏蔽方法
公开(公告)号：US20050201152A1
公开(公告)日：2005-09-15
申请号：US10797156
申请日：2004-03-09
申请人： Hung Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
发明人： Hung Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
IPC分类号： G11C15/00 , G11C16/06 , G11C29/00
CPC分类号： G11C29/024
摘要： A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.
摘要翻译：用于屏蔽非易失性存储器阵列中可寻址线路中的缺陷的电路包括具有多个镜像级的电流镜电路。电流镜电路连接到可寻址线路并接收控制信号并镜像控制信号以向可寻址线路提供电流。在优选实施例中，电流镜电路向可寻址线路提供高电压电流，该可寻址线路用于对连接到可寻址线路的存储器单元实现诸如编程或擦除的操作。连接到可寻址线路的存储器单元的状态变化或不存在状态的变化可用于筛选可寻址线路中的缺陷。

4. 发明申请

US20070070703A1 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US20070070703A1
公开(公告)日：2007-03-29
申请号：US11235901
申请日：2005-09-26
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

5. 发明申请

US20070250744A1 Method and apparatus for testing the connectivity of a flash memory chip 有权
标题翻译：用于测试闪存芯片连接性的方法和装置
公开(公告)号：US20070250744A1
公开(公告)日：2007-10-25
申请号：US11407602
申请日：2006-04-19
申请人： Sang Nguyen , Hieu Tran , Hung Nguyen , Phil Klotzkin
发明人： Sang Nguyen , Hieu Tran , Hung Nguyen , Phil Klotzkin
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
摘要翻译：在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。该测试电路电连接到IC的接合焊盘。在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。然后检索顺序发送的数据并将其与原始数据进行比较。因此，这些数据集之间的差异突出了IC中的连接问题。

6. 发明申请

US20060202668A1 Fast voltage regulators for charge pumps 有权
公开(公告)号：US20060202668A1
公开(公告)日：2006-09-14
申请号：US11080070
申请日：2005-03-14
申请人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
发明人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
IPC分类号： G05F5/00 , G05F1/00
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

7. 发明申请

US20050249006A1 Low voltage high speed sensing 有权
标题翻译：低电压高速感应
公开(公告)号：US20050249006A1
公开(公告)日：2005-11-10
申请号：US10838999
申请日：2004-05-04
申请人： Hieu Tran , Sang Nguyen , Hung Nguyen
发明人： Hieu Tran , Sang Nguyen , Hung Nguyen
IPC分类号： G11C7/00 , G11C7/06 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

8. 发明申请

US20060123280A1 Test circuit and method for multilevel cell flash memory 有权
公开(公告)号：US20060123280A1
公开(公告)日：2006-06-08
申请号：US10991702
申请日：2004-11-17
申请人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
发明人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

9. 发明申请

US20070147131A1 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US20070147131A1
公开(公告)日：2007-06-28
申请号：US11707341
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

10. 发明申请

US20070147111A1 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US20070147111A1
公开(公告)日：2007-06-28
申请号：US11707343
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式