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1. 发明授权

US09383801B2 Methods and apparatus related to processor sleep states 有权
标题翻译：与处理器睡眠状态有关的方法和设备
公开(公告)号：US09383801B2
公开(公告)日：2016-07-05
申请号：US13725014
申请日：2012-12-21
申请人： Alexander J. Branover , Andrew W. Lueck , Paul E. Kitchin , David A. Kaplan
发明人： Alexander J. Branover , Andrew W. Lueck , Paul E. Kitchin , David A. Kaplan
IPC分类号： G06F1/32
CPC分类号： G06F1/3234
摘要： A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.
摘要翻译：系统包括处理器，该处理器至少包括与第一核心相关联的第一核心和本地中断控制器。第一核心可操作以在进入第一核心睡眠状态之前存储其架构状态，并且处理器可操作以接收和实施用于进入其中第一核心处于第一核心睡眠状态的系统睡眠状态的请求，局部中断控制器掉电并退出系统休眠状态，通过恢复本地中断控制器并恢复第一个内核的保存架构状态。

2. 发明申请

US20140181557A1 METHODS AND APPARATUS RELATED TO PROCESSOR SLEEP STATES 有权
标题翻译：与处理器休眠状态相关的方法和装置
公开(公告)号：US20140181557A1
公开(公告)日：2014-06-26
申请号：US13725014
申请日：2012-12-21
申请人： Alexander J. Branover , Andrew W. Lueck , Paul E. Kitchin , David A. Kaplan
发明人： Alexander J. Branover , Andrew W. Lueck , Paul E. Kitchin , David A. Kaplan
IPC分类号： G06F1/32
CPC分类号： G06F1/3234
摘要： A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.
摘要翻译：系统包括处理器，该处理器至少包括与第一核心相关联的第一核心和本地中断控制器。第一核心可操作以在进入第一核心睡眠状态之前存储其架构状态，并且处理器可操作以接收和实施用于进入其中第一核心处于第一核心睡眠状态的系统睡眠状态的请求，局部中断控制器掉电并退出系统休眠状态，通过恢复本地中断控制器并恢复第一个内核的保存架构状态。

3. 发明授权

US09423847B2 Method and apparatus for transitioning a system to an active disconnect state 有权
标题翻译：用于将系统转换到主动断开状态的方法和装置
公开(公告)号：US09423847B2
公开(公告)日：2016-08-23
申请号：US13332280
申请日：2011-12-20
申请人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
发明人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206
摘要： A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
摘要翻译：处理器包括处理器核心和功率管理控制器，其可操作以接收定时器事件，存储定时器事件，生成硬件系统睡眠命令以进入硬件系统睡眠状态，以及在退出硬件系统睡眠状态时恢复定时器事件。

4. 发明授权

US08862909B2 System and method for determining a power estimate for an I/O controller based on monitored activity levels and adjusting power limit of processing units by comparing the power estimate with an assigned power limit for the I/O controller 有权
标题翻译：通过将功率估计与I / O控制器的分配的功率限制进行比较，基于监视的活动水平和调整处理单元的功率限制来确定I / O控制器的功率估计的系统和方法
公开(公告)号：US08862909B2
公开(公告)日：2014-10-14
申请号：US13310231
申请日：2011-12-02
申请人： Alexander J. Branover , Madhu Saravana Sibi Govindan , Guhan Krishnan , Hemant R. Mohapatra , Andrew W. Lueck
发明人： Alexander J. Branover , Madhu Saravana Sibi Govindan , Guhan Krishnan , Hemant R. Mohapatra , Andrew W. Lueck
IPC分类号： G06F1/00 , G06F1/32 , G06F1/26
CPC分类号： G06F1/32 , G06F1/00 , G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A system and method for efficient management of operating modes within an IC for optimal power and performance targets. On a same die, an SOC includes one or more processing units and a input/output (I/O) controller (IOC). The multiple interfaces within the IOC manage packets and messages according multiple different protocols. The IOC maintains an activity level for each one of the multiple interfaces. This activity level may be based at least on a respective number of transactions executed by a corresponding one of the multiple interfaces. The IOC determines a power estimate for itself based on at least the activity levels. In response to detecting a difference between the power estimate and an assigned I/O power limit for the IOC, a power manager adjusts at least respective power limits for the one or more processing units based on at least the difference.
摘要翻译：一种用于高效管理IC内的运行模式以实现最佳功率和性能目标的系统和方法。在相同的芯片上，SOC包括一个或多个处理单元和输入/输出（I / O）控制器（IOC）。 IOC中的多个接口根据多种不同的协议管理数据包和消息。 IOC维护多个接口中的每一个的活动级别。该活动级别可以至少基于由多个接口中的相应一个执行的事务的相应数量。至少基于活动水平，国际奥委会决定自己的能力估计。响应于检测到功率估计与IOC的分配的I / O功率限制之间的差异，功率管理器至少基于差异来调整至少相应的一个或多个处理单元的功率限制。

5. 发明申请

US20130145180A1 METHOD OF POWER CALCULATION FOR PERFORMANCE OPTIMIZATION 有权
标题翻译：用于性能优化的功率计算方法
公开(公告)号：US20130145180A1
公开(公告)日：2013-06-06
申请号：US13310231
申请日：2011-12-02
申请人： Alexander J. Branover , Madhu Saravana Sibi Govindan , Guhan Krishnan , Hemant R. Mohapatra , Andrew W. Lueck
发明人： Alexander J. Branover , Madhu Saravana Sibi Govindan , Guhan Krishnan , Hemant R. Mohapatra , Andrew W. Lueck
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/00 , G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A system and method for efficient management of operating modes within an IC for optimal power and performance targets. On a same die, an SOC includes one or more processing units and a input/output (I/O) controller (IOC). The multiple interfaces within the IOC manage packets and messages according multiple different protocols. The IOC maintains an activity level for each one of the multiple interfaces. This activity level may be based at least on a respective number of transactions executed by a corresponding one of the multiple interfaces. The IOC determines a power estimate for itself based on at least the activity levels. In response to detecting a difference between the power estimate and an assigned I/O power limit for the IOC, a power manager adjusts at least respective power limits for the one or more processing units based on at least the difference.
摘要翻译：一种用于高效管理IC内的运行模式以实现最佳功率和性能目标的系统和方法。在相同的芯片上，SOC包括一个或多个处理单元和输入/输出（I / O）控制器（IOC）。 IOC中的多个接口根据多种不同的协议管理数据包和消息。 IOC维护多个接口中的每一个的活动级别。该活动级别可以至少基于由多个接口中的相应一个执行的事务的相应数量。至少基于活动水平，国际奥委会决定自己的能力估计。响应于检测到功率估计与IOC的分配的I / O功率限制之间的差异，功率管理器至少基于差异来调整至少相应的一个或多个处理单元的功率限制。

6. 发明申请

US20130159750A1 METHOD AND APPARATUS FOR TRANSITIONING A SYSTEM TO AN ACTIVE DISCONNECT STATE 有权
标题翻译：将系统过渡到活动断开状态的方法和装置
公开(公告)号：US20130159750A1
公开(公告)日：2013-06-20
申请号：US13332280
申请日：2011-12-20
申请人： Alexander J. Branover , Krishna S. Bernucho , Maurice B. Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L. Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P. Shimizu , Gary H. Simpson , Laura M. Smith
发明人： Alexander J. Branover , Krishna S. Bernucho , Maurice B. Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L. Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P. Shimizu , Gary H. Simpson , Laura M. Smith
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206
摘要： A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
摘要翻译：处理器包括处理器核心和功率管理控制器，其可操作以接收定时器事件，存储定时器事件，生成硬件系统睡眠命令以进入硬件系统睡眠状态，以及在退出硬件系统睡眠状态时恢复定时器事件。

7. 发明授权

US07543131B2 Controlling an I/O MMU 有权
标题翻译：控制I / O MMU
公开(公告)号：US07543131B2
公开(公告)日：2009-06-02
申请号：US11503390
申请日：2006-08-11
申请人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael J. Haertel
发明人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael J. Haertel
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F12/1027 , G06F12/145
摘要： In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configured to implement address translation and memory protection for memory operations sourced by one or more input/output (I/O) devices. The memory stores a command queue during use. The memory management module is configured to write one or more control commands to the command queue, and the IOMMU is configured to read the control commands from the command queue and execute the control commands.
摘要翻译：在一个实施例中，计算机系统包括处理器; 存储器管理模块，包括可在所述处理器上执行的多个指令; 耦合到处理器的存储器; 以及耦合到存储器的输入/输出存储器管理单元（IOMMU）。 IOMMU被配置为对由一个或多个输入/输出（I / O）设备提供的存储器操作实现地址转换和存储器保护。内存在使用过程中存储命令队列。存储器管理模块被配置为将一个或多个控制命令写入命令队列，并且IOMMU被配置为从命令队列读取控制命令并执行控制命令。

8. 发明授权

US07516247B2 Avoiding silent data corruption and data leakage in a virtual environment with multiple guests 有权
标题翻译：避免在具有多个guest虚拟机的虚拟环境中静默的数据损坏和数据泄露
公开(公告)号：US07516247B2
公开(公告)日：2009-04-07
申请号：US11503391
申请日：2006-08-11
申请人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael J. Haertel
发明人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael J. Haertel
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00
CPC分类号： G06F12/1081 , G06F12/1027 , G06F2212/683
摘要： In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed by the IOMMU prior to a completion of the completion wait command. The IOMMU is configured to respond to the completion wait command by delaying completion of the completion wait command until: (1) a read response corresponding to each outstanding memory read operation that depends on a translation entry that is invalidated by the preceding invalidation commands is received; and (2) the control unit transmits one or more operations upstream to ensure that each memory write operation that depends on the translation table entry that is invalidated by the preceding invalidation commands has at least reached a bridge to a coherent fabric in the computer system and has become visible to the system.
摘要翻译：在一个实施例中，输入/输出存储器管理单元（IOMMU）被配置为接收定义的完成等待命令，以在完成等待命令完成之前确保由IOMMU完成一个或多个以前的无效命令。 IOMMU被配置为通过延迟完成等待命令的完成来响应完成等待命令，直到：（1）接收与取决于由前述无效命令无效的转换条目的每个未完成存储器读操作对应的读响应 ; （2）控制单元向上游发送一个或多个操作，以确保依赖于由前述无效命令无效的转换表项的每个存储器写入操作至少达到计算机系统中的相干结构的桥接，以及已经变得对系统可见。

9. 发明申请

US20070168641A1 Virtualizing an IOMMU 有权
标题翻译：虚拟化IOMMU
公开(公告)号：US20070168641A1
公开(公告)日：2007-07-19
申请号：US11623626
申请日：2007-01-16
申请人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel
发明人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel
IPC分类号： G06F12/00
CPC分类号： G06F9/45558 , G06F2009/45579 , G06F2009/45583
摘要： In one embodiment, a system comprises one or more input/output (I/O) devices; an I/O memory management unit (IOMMU) coupled to receive memory requests sourced by the I/O devices and configured to provide address translation for the memory requests; and a virtual machine monitor (VMM) configured to manage one or more virtual machines on the system, wherein the VMM is configured to virtualize the IOMMU, providing one or more virtual IOMMUs for use by one or more virtual machines.
摘要翻译：在一个实施例中，系统包括一个或多个输入/输出（I / O）设备; I / O存储器管理单元（IOMMU），其耦合以接收由所述I / O设备提供的存储器请求，并被配置为提供所述存储器请求的地址转换; 以及被配置为管理所述系统上的一个或多个虚拟机的虚拟机监视器（VMM），其中所述VMM被配置为虚拟化所述IOMMU，提供一个或多个虚拟IOMMU供一个或多个虚拟机使用。

10. 发明申请

US20070168643A1 DMA Address Translation in an IOMMU 有权
标题翻译： DMA地址转换在IOMMU
公开(公告)号：US20070168643A1
公开(公告)日：2007-07-19
申请号：US11623500
申请日：2007-01-16
申请人： Mark D. Hummel , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel , Andrew W. Lueck
发明人： Mark D. Hummel , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel , Andrew W. Lueck
IPC分类号： G06F12/00
CPC分类号： G06F12/1081
摘要： In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.
摘要翻译：在一个实施例中，输入/输出（I / O）存储器管理单元（IOMMU）包括被配置为存储转换数据的至少一个存储器; 以及控制逻辑，其耦合到所述存储器并且被配置为使用所述翻译数据来转换I / O设备生成的存储器请求。翻译数据对应于存储在包括IOMMU的计算机系统的存储器系统中的设备表中的一个或多个设备表条目，其中给定请求的设备表条目由对应于I / O设备的标识符选择生成请求。翻译数据还对应于一个或多个I / O页表，其中用于给定请求的所选择的设备表条目包括指向要用于转换给定请求的一组I / O页表的指针。

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