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1. 发明授权

US09423847B2 Method and apparatus for transitioning a system to an active disconnect state 有权
标题翻译：用于将系统转换到主动断开状态的方法和装置
公开(公告)号：US09423847B2
公开(公告)日：2016-08-23
申请号：US13332280
申请日：2011-12-20
申请人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
发明人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206
摘要： A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
摘要翻译：处理器包括处理器核心和功率管理控制器，其可操作以接收定时器事件，存储定时器事件，生成硬件系统睡眠命令以进入硬件系统睡眠状态，以及在退出硬件系统睡眠状态时恢复定时器事件。

2. 发明授权

US09417679B2 Adaptive connected standby for a computing device 有权
标题翻译：计算设备的自适应连接待机
公开(公告)号：US09417679B2
公开(公告)日：2016-08-16
申请号：US13674476
申请日：2012-11-12
申请人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
发明人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
IPC分类号： G06F1/32
CPC分类号： G06F1/3212 , G06F1/3287 , Y02D10/171 , Y02D10/174
摘要： Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery.
摘要翻译：公开了各种计算设备和管理功耗的方法。一方面，提供一种管理具有电池的计算装置的功耗的方法。该方法包括在连接的待机活动状态和连接的待机空闲状态之间循环计算设备。连接的待机空闲状态的持续时间至少部分地基于电池的充电水平来设定。

3. 发明授权

US08924758B2 Method for SOC performance and power optimization 有权
标题翻译： SOC性能和功率优化方法
公开(公告)号：US08924758B2
公开(公告)日：2014-12-30
申请号：US13360012
申请日：2012-01-27
申请人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
发明人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.
摘要翻译：一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。诸如片上系统（SOC）的集成电路包括至少两个处理单元。第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

4. 发明申请

US20130151869A1 METHOD FOR SOC PERFORMANCE AND POWER OPTIMIZATION 有权
标题翻译：用于SOC性能和功率优化的方法
公开(公告)号：US20130151869A1
公开(公告)日：2013-06-13
申请号：US13360012
申请日：2012-01-27
申请人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
发明人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.
摘要翻译：一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。诸如片上系统（SOC）的集成电路包括至少两个处理单元。第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

5. 发明授权

US08112648B2 Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state 有权
标题翻译：加强对CPU驻留和线程重新调度的控制，以最大限度地发挥低功耗状态的优势
公开(公告)号：US08112648B2
公开(公告)日：2012-02-07
申请号：US12333744
申请日：2008-12-12
申请人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
发明人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
IPC分类号： G06F1/26
CPC分类号： G06F9/5027 , G06F1/3203 , G06F1/3296 , G06F9/5094 , G06F2209/508 , Y02D10/172 , Y02D10/22
摘要： A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.
摘要翻译：系统可以包括多个处理单元和被配置为维护每个相应处理单元的记录的调度器。每个相应的记录可以包括可以指示1）各个处理单元已经驻留在空闲状态多长时间的条目，2）相应处理单元驻留的当前功率状态，以及3）各个处理单元是否为指定默认（bootstrap）处理单元。调度器可以根据它们各自的记录来选择多个处理单元中的一个或多个，并分配要在所选择的一个或多个处理单元上执行的即将发生的指令。在需要附加处理单元的情况下，调度器还可以插入用于触发处理器间中断以将一个或多个处理单元转变为空闲状态的指令。然后，调度器可以向这些一个或多个处理单元分配一些即将发生的指令。

6. 发明申请

US20110283124A1 METHOD AND APPARATUS FOR CACHE CONTROL 有权
标题翻译：缓存控制的方法和设备
公开(公告)号：US20110283124A1
公开(公告)日：2011-11-17
申请号：US12777657
申请日：2010-05-11
申请人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
发明人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
摘要翻译：公开了一种用于动态控制高速缓存大小的方法和装置。在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

7. 发明申请

US20110264934A1 METHOD AND APPARATUS FOR MEMORY POWER MANAGEMENT 有权
标题翻译：用于存储电源管理的方法和装置
公开(公告)号：US20110264934A1
公开(公告)日：2011-10-27
申请号：US12767460
申请日：2010-04-26
申请人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
发明人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
摘要翻译：公开了一种用于电力管理的方法。该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量内存访问请求。如果第一和第二时间量已经过去，则可以断言第一信号。存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

8. 发明授权

US07844767B2 Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link 有权
标题翻译：用于识别通过链路连接的两个CSI代理的不良通道和交换宽度能力的方法
公开(公告)号：US07844767B2
公开(公告)日：2010-11-30
申请号：US10851925
申请日：2004-05-21
申请人： Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn , Rahul R. Shah , Maurice B. Steinman
发明人： Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn , Rahul R. Shah , Maurice B. Steinman
IPC分类号： G06F13/42 , G06F13/14 , G06F11/00
CPC分类号： G06F13/4265
摘要： A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link width that is mutually agreeable. The interconnect between each pair of agents comprises a pair of uni-directional links having multiple electrical wires, or lanes, where one link is used by a first agent to transmit data to a second agent and another link is used by the second agent to transmit data to the first agent.
摘要翻译：描述了一种技术，其中具有使用系统中的点对点互连耦合在一起的端口的两个链路代理交换其链路宽度支持能力并协商相互同意的链路宽度。每对代理之间的互连包括具有多个电线或通道的一对单向链路，其中一个链路被第一代理用于向第二代理传输数据，另一链路由第二代理使用，数据到第一代理。

9. 发明授权

US07568118B2 Deterministic operation of an input/output interface 有权
标题翻译：输入/输出接口的确定性操作
公开(公告)号：US07568118B2
公开(公告)日：2009-07-28
申请号：US11231273
申请日：2005-09-20
申请人： Warren R. Anderson , Maurice B. Steinman , Richard M. Watson , Horst W. Wagner , Christopher C. Gianos , Suresh Balasubramanian , Tim Frodsham
发明人： Warren R. Anderson , Maurice B. Steinman , Richard M. Watson , Horst W. Wagner , Christopher C. Gianos , Suresh Balasubramanian , Tim Frodsham
IPC分类号： G06F13/42 , H04L5/00
CPC分类号： H04L7/00 , H04L7/0008 , H04L7/005
摘要： In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从第一设备中的第二设备接收数据的方法，将数据从输入/输出（I / O）时钟域转发到第一设备的系统时钟域，在确定性时间将数据传送到第一设备的功能单元。以这种方式，两个装置可以锁定方式操作。描述和要求保护其他实施例。

10. 发明授权

US07362739B2 Methods and apparatuses for detecting clock failure and establishing an alternate clock lane 有权
标题翻译：用于检测时钟故障并建立备用时钟通道的方法和装置
公开(公告)号：US07362739B2
公开(公告)日：2008-04-22
申请号：US10874511
申请日：2004-06-22
申请人： Naveen Cherukuri , Tim Frodsham , Eduard Roytman , Sanjay Dabral , Rahul Shah , Theodore Z. Schoenborn , Maurice B. Steinman , David S. Dunning
发明人： Naveen Cherukuri , Tim Frodsham , Eduard Roytman , Sanjay Dabral , Rahul Shah , Theodore Z. Schoenborn , Maurice B. Steinman , David S. Dunning
IPC分类号： H04B7/216
CPC分类号： H04J3/0688 , H04L43/00 , H04L43/0847
摘要： Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.
摘要翻译：用于确定使用转发时钟的基于链路的互连方案的多代理系统的时钟故障的方法和装置。对于本发明的一个实施例，转发时钟的停止启动时钟失败确定过程。对于本发明的一个实施例，在确定时钟故障时，使用预先指定的数据通道实现备用时钟通道。

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