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1. 发明授权

US06507939B1 Net delay optimization with ramptime violation removal 有权
标题翻译：净延迟优化与删除违反时间违规
公开(公告)号：US06507939B1
公开(公告)日：2003-01-14
申请号：US09858166
申请日：2001-05-15
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Igor A. Vikhliantsev
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Igor A. Vikhliantsev
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.
摘要翻译：该说明书公开了一种用于在具有根和多个叶的逻辑树中减少净延迟和缓冲器的插入。该方法的步骤包括将多个辅助节点插入到定义离散的近似尺度以用于延迟，加载和斜坡时间，构建一组缓冲器链以供稍后插入到网络树中，确定树上的每个节点与每个节点相关的斜坡时间，出发时间和节点处的负载的折衷函数，去除折中功能和缓冲链的组合，当组合被插入到权衡函数中时，导致超过预定的最大允许斜坡的斜坡时间时间，对于每个节点，使用权衡函数来确定插入的最小延迟，以及插入对应于由权衡函数确定的最小延迟的缓冲链。

2. 发明授权

US07062726B2 Method for generating tech-library for logic function 失效
标题翻译：用于生成逻辑功能的技术库的方法
公开(公告)号：US07062726B2
公开(公告)日：2006-06-13
申请号：US10426549
申请日：2003-04-30
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Anatoli A. Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library. When the number of elements in the tech-library is at least twice larger than a limit, the number is reduced.
摘要翻译：本发明涉及一种用于生成用于逻辑功能的技术库的方法。逻辑函数有很多表示。对于每个表示，用于实现表示的电路被分解为实例的组合。实例是通用逻辑电路的分量逻辑电路。这些实例有预先创建的技术库。例如，通过基于否定索引对原始物理电路的技术描述进行分类来创建预先创建的技术库。因此，用于实现表示的电路的技术描述由预先创建的技术库的元素的组合计算。将每个计算的技术描述与逻辑功能的技术库的每个现有元素进行比较。当计算出的技术描述至少有一个比逻辑功能的技术库的所有现有元素更好或更小的标记参数时，计算出的技术描述被添加到技术库。当技术库中的元素数量至少比限制大两倍时，数量就会减少。

3. 发明授权

US07856577B2 Command language for memory testing 有权
标题翻译：内存测试的命令语言
公开(公告)号：US07856577B2
公开(公告)日：2010-12-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

4. 发明授权

US07231383B2 Search engine for large-width data 有权
标题翻译：大型数据搜索引擎
公开(公告)号：US07231383B2
公开(公告)日：2007-06-12
申请号：US10137874
申请日：2002-05-01
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F9/342 , Y10S707/99931 , Y10S707/99933 , Y10S707/99934
摘要： A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.
摘要翻译：搜索引擎架构将短索引替换为大数据宽度，从而减少输入到搜索引擎输出所需的宽度。搜索引擎系统包括响应于输入地址以访问搜索引擎中的索引的搜索引擎。该索引具有不大于搜索引擎容量的基础2上的对数的宽度，从而允许搜索引擎体现在缩小区域的IC芯片中。驱动程序响应输入命令和搜索引擎状态来管理搜索引擎中的索引，并使内存能够基于搜索引擎中的索引访问其可寻址位置。

5. 发明授权

US06662287B1 Fast free memory address controller 失效
标题翻译：快速可用内存地址控制器
公开(公告)号：US06662287B1
公开(公告)日：2003-12-09
申请号：US10000243
申请日：2001-10-18
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F1200
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99956
摘要： A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.
摘要翻译：用于管理存储器中的地址分配的存储器管理器被构造为具有顶部顶点，底部水平和至少一个中间水平的分层树。底层包含多个底部顶点，每个底部顶点包含多个存储器中相应地址的自由或取代状态的表示。每个中间体包含至少一个包含多个标签的层次顶点，使得每个标签与子顶点相关联，并且定义包含相应子顶点的路径是否包含在包含至少一个自由表示的相应底层顶点中。一个分配命令将第一个自由地址的表示更改为Taken，一个free命令将指定地址的表示更改为Free。更改层次顶点中的标签以反映底层顶点的路径条件。

6. 发明授权

US07283385B2 RRAM communication system 失效
标题翻译： RRAM通信系统
公开(公告)号：US07283385B2
公开(公告)日：2007-10-16
申请号：US10999481
申请日：2004-11-30
申请人： Alexander E. Andreev , Sergey Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/4401 , G11C29/56004 , G11C2029/3602 , G11C2029/5602
摘要： The present invention provides a RRAM communication system including at least one RRAM controller and a master controller. The master controller is communicatively coupled to each of at least one RRAM controller. The master controller is suitable for loading test input parameters into at least one RRAM controller, starting execution of a test and obtaining a result of test execution from at least one RRAM controller. Each of at least one RRAM controller is suitable for executing different tests depending on commands received from the master controller.
摘要翻译：本发明提供一种包括至少一个RRAM控制器和主控制器的RRAM通信系统。主控制器通信地耦合到至少一个RRAM控制器中的每一个。主控制器适用于将测试输入参数加载到至少一个RRAM控制器中，开始执行测试并从至少一个RRAM控制器获得测试执行结果。至少一个RRAM控制器中的每一个适合于根据从主控制器接收到的命令执行不同的测试。

7. 发明授权

US07200785B2 Sequential tester for longest prefix search engines 有权
公开(公告)号：US07200785B2
公开(公告)日：2007-04-03
申请号：US10387988
申请日：2003-03-13
申请人： Alexander E. Andreev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Anatoli A. Bolotov
IPC分类号： G01R31/28
CPC分类号： G01R31/31917 , Y10S707/99933
摘要： The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.

8. 发明授权

US07082561B2 Built-in functional tester for search engines 失效
公开(公告)号：US07082561B2
公开(公告)日：2006-07-25
申请号：US10135624
申请日：2002-04-30
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Nikola Radovanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Nikola Radovanovic
IPC分类号： G01R31/28
CPC分类号： G01R31/3183 , G01R31/318378
摘要： A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.

9. 发明授权

US06453453B1 Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes 有权
标题翻译：用单向对象惩罚函数和线性有序集合集合来解决集成电路设计中的赋值问题的过程
公开(公告)号：US06453453B1
公开(公告)日：2002-09-17
申请号：US09833142
申请日：2001-04-11
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Pedja Raspopovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Pedja Raspopovic
IPC分类号： G06F945
CPC分类号： G06F17/5068
摘要： A linear assignment problem for an ordered system containing a plurality of boxes each containing an object having an associated penalty function is solved. A hierarchy contains a bottom level containing at least as many generalized boxes as there are boxes in the assignment problem, and top and intermediate levels. The objects of the assignment problem are placed in the generalized box of the top level. A first local task is executed to transition the contents of a generalized box of a higher level to at least two generalized boxes of the next lower level. A second local task is executed on the generalized boxes of the lower level to minimize a global penalty function. The first and second tasks are executed through successive iterations until all of the objects are placed in the generalized boxes in the bottom level in a layout having minimal penalty function.
摘要翻译：解决了包含多个框的有序系统的线性分配问题，每个框包含具有相关惩罚函数的对象。层次结构包含底层，包含至少与分配问题中的框以及顶级和中级相同的通用框。分配问题的对象被放置在顶层的广义框中。执行第一本地任务以将较高级别的广义框的内容转换到下一较低级的至少两个广义框。在较低级别的广义框上执行第二个本地任务，以最小化全局惩罚函数。第一和第二任务通过连续迭代执行，直到所有对象都放置在具有最小惩罚函数的布局中的底层中的广义框中。

10. 发明授权

US08132075B2 Memory mapping for parallel turbo decoding 失效
标题翻译：并行turbo解码的内存映射
公开(公告)号：US08132075B2
公开(公告)日：2012-03-06
申请号：US11924385
申请日：2007-10-25
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译：路由复用器系统基于所选择的p个输入的排列来提供p个输出。多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。多个控制位表各自包含基于相应置换的布置中的多个位。存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。

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