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1. 发明授权

US06507939B1 Net delay optimization with ramptime violation removal 有权
标题翻译：净延迟优化与删除违反时间违规
公开(公告)号：US06507939B1
公开(公告)日：2003-01-14
申请号：US09858166
申请日：2001-05-15
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Igor A. Vikhliantsev
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Igor A. Vikhliantsev
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.
摘要翻译：该说明书公开了一种用于在具有根和多个叶的逻辑树中减少净延迟和缓冲器的插入。该方法的步骤包括将多个辅助节点插入到定义离散的近似尺度以用于延迟，加载和斜坡时间，构建一组缓冲器链以供稍后插入到网络树中，确定树上的每个节点与每个节点相关的斜坡时间，出发时间和节点处的负载的折衷函数，去除折中功能和缓冲链的组合，当组合被插入到权衡函数中时，导致超过预定的最大允许斜坡的斜坡时间时间，对于每个节点，使用权衡函数来确定插入的最小延迟，以及插入对应于由权衡函数确定的最小延迟的缓冲链。

2. 发明授权

US07062726B2 Method for generating tech-library for logic function 失效
标题翻译：用于生成逻辑功能的技术库的方法
公开(公告)号：US07062726B2
公开(公告)日：2006-06-13
申请号：US10426549
申请日：2003-04-30
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Anatoli A. Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library. When the number of elements in the tech-library is at least twice larger than a limit, the number is reduced.
摘要翻译：本发明涉及一种用于生成用于逻辑功能的技术库的方法。逻辑函数有很多表示。对于每个表示，用于实现表示的电路被分解为实例的组合。实例是通用逻辑电路的分量逻辑电路。这些实例有预先创建的技术库。例如，通过基于否定索引对原始物理电路的技术描述进行分类来创建预先创建的技术库。因此，用于实现表示的电路的技术描述由预先创建的技术库的元素的组合计算。将每个计算的技术描述与逻辑功能的技术库的每个现有元素进行比较。当计算出的技术描述至少有一个比逻辑功能的技术库的所有现有元素更好或更小的标记参数时，计算出的技术描述被添加到技术库。当技术库中的元素数量至少比限制大两倍时，数量就会减少。

3. 发明授权

US07856577B2 Command language for memory testing 有权
标题翻译：内存测试的命令语言
公开(公告)号：US07856577B2
公开(公告)日：2010-12-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

4. 发明授权

US07231383B2 Search engine for large-width data 有权
标题翻译：大型数据搜索引擎
公开(公告)号：US07231383B2
公开(公告)日：2007-06-12
申请号：US10137874
申请日：2002-05-01
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F9/342 , Y10S707/99931 , Y10S707/99933 , Y10S707/99934
摘要： A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.
摘要翻译：搜索引擎架构将短索引替换为大数据宽度，从而减少输入到搜索引擎输出所需的宽度。搜索引擎系统包括响应于输入地址以访问搜索引擎中的索引的搜索引擎。该索引具有不大于搜索引擎容量的基础2上的对数的宽度，从而允许搜索引擎体现在缩小区域的IC芯片中。驱动程序响应输入命令和搜索引擎状态来管理搜索引擎中的索引，并使内存能够基于搜索引擎中的索引访问其可寻址位置。

5. 发明授权

US06662287B1 Fast free memory address controller 失效
标题翻译：快速可用内存地址控制器
公开(公告)号：US06662287B1
公开(公告)日：2003-12-09
申请号：US10000243
申请日：2001-10-18
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F1200
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99956
摘要： A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.
摘要翻译：用于管理存储器中的地址分配的存储器管理器被构造为具有顶部顶点，底部水平和至少一个中间水平的分层树。底层包含多个底部顶点，每个底部顶点包含多个存储器中相应地址的自由或取代状态的表示。每个中间体包含至少一个包含多个标签的层次顶点，使得每个标签与子顶点相关联，并且定义包含相应子顶点的路径是否包含在包含至少一个自由表示的相应底层顶点中。一个分配命令将第一个自由地址的表示更改为Taken，一个free命令将指定地址的表示更改为Free。更改层次顶点中的标签以反映底层顶点的路径条件。

6. 发明授权

US08132075B2 Memory mapping for parallel turbo decoding 失效
标题翻译：并行turbo解码的内存映射
公开(公告)号：US08132075B2
公开(公告)日：2012-03-06
申请号：US11924385
申请日：2007-10-25
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译：路由复用器系统基于所选择的p个输入的排列来提供p个输出。多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。多个控制位表各自包含基于相应置换的布置中的多个位。存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。

7. 发明授权

US07548844B2 Sequential tester for longest prefix search engines 失效
标题翻译：最长前缀搜索引擎的顺序测试器
公开(公告)号：US07548844B2
公开(公告)日：2009-06-16
申请号：US11706943
申请日：2007-02-13
申请人： Alexander E. Andreev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Anatoli A. Bolotov
IPC分类号： G06F9/45
CPC分类号： G01R31/31917 , Y10S707/99933
摘要： The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.
摘要翻译：本发明涉及一种用于最长前缀搜索引擎的顺序测试器。测试器可以包括最长的前缀搜索引擎，用于向最长的前缀搜索引擎提供几乎随机的输入命令的输入生成器，并输出可以表示最长前缀搜索引擎的搜索表的浮动矩形，编码模块用于向最长前缀搜索引擎提供地址和前缀信息，用于向最长前缀搜索引擎提供数据信息的映射模块，用于执行超级搜索操作的超级搜索引擎和用于计算最长前缀搜索引擎的预测输出的分析器并将预测输出与由最长前缀搜索引擎计算的实际输出进行比较。

8. 发明授权

US07430694B2 Memory BISR architecture for a slice 有权
标题翻译：内存BISR架构为一片
公开(公告)号：US07430694B2
公开(公告)日：2008-09-30
申请号：US11038698
申请日：2005-01-20
申请人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00 , G06F12/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2, . . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f—1, f—2, . . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r—1, r—2, . . . , r_n); and (5) a FUSE module, communicatively coupled to the BISR controller and the REPAIR_CONFIGURATION module, for storing the repair configuration vector R. The REPAIR_CONFIGURATION module, communicatively coupled to the plurality of physical memory instances M_i and an integrated circuit design D, includes switch module instances S for switching among the plurality of physical memory instances in accordance with the repair configuration vector R. The ROM module stores a vector U indicating usage of the plurality of physical memory instances M_i by the integrated circuit design D.
摘要翻译：本发明提供了一种用于切片的存储器BISR架构。该架构包括（1）多个物理存储器实例; （2）通信地耦合到所述多个物理存储器实例的用于测试所述多个物理存储器实例的Mem_BIST控制器; （3）FLARE模块，通信地耦合到所述Mem_BIST控制器，包括用于存储所述多个物理存储器实例的测试结果的寄存器扫描链，所述多个物理存储器实例M_i中的每一个被分配一个FLARE位f_i，i = 1，2，... 。。，n，由Mem_BIST控制器使用的FLARE模块以错误向量F =（f 1 - 1，f 2 - ，...，f_n）进行扫描; （4）通信地耦合到FLARE模块的BISR控制器，ROM模块和REPAIR_CONFIGURATION模块，用于从FLARE模块向计算机扫描出错误向量F，修复配置向量R =（r - > 1，r 2，...，r_n）; 和（5）通信地耦合到BISR控制器和REPAIR_CONFIGURATION模块的FUSE模块，用于存储修复配置向量R.通信地耦合到多个物理存储器实例M_i和集成电路设计D的REPAIR_CONFIGURATION模块包括开关模块实例S，用于根据修复配置向量R在多个物理存储器实例之间切换.ROM模块通过集成电路设计D存储指示多个物理存储器实例M_i的使用的向量U。

9. 发明授权

US07328382B2 Memory BISR controller architecture 失效
标题翻译：内存BISR控制器架构
公开(公告)号：US07328382B2
公开(公告)日：2008-02-05
申请号：US11270077
申请日：2005-11-09
申请人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/44 , G06F11/00 , G11C29/4401 , G11C29/72
摘要： The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN input port and a BISR_IN input port for setting configuration of the memory BISR controller. Each of the N groups of data ports includes (1) a PHY_IN output port for connecting to input of a corresponding memory instance; (2) a PHY_OUT input port for connecting to output of the corresponding memory instance; (3) a LOG_IN input port for sending signals to the corresponding memory instance; and (4) a LOG_OUT output port for receiving signals from the corresponding memory instance. Each of the N BISR_SUBMOD modules includes a flip-flop, a first mux and a second mux. The CLK_IN input port is connected to clock inputs of all N flip-flops of the memory BISR controller. The BISR_IN input port is connected to data input of a first flip-flop, and output of a K-th flip-flop is connected to input of a (K+1)-th flip-flop, K=1, 2, . . . , N-1. When at least one of the N memory instances is defective, the memory BISR controller may reconfigure connections among the N memory instances to use other memory instance(s) instead of the defective memory instance(s).
摘要翻译：本发明提供了一种用于连接到N个存储器实例的存储器内置自修复（BISR）控制器的架构，其中N是大于1的正整数。该架构包括N组数据端口，N个BISR_SUBMOD模块用于连接到 N个内存实例，以及用于设置内存BISR控制器配置的CLK_IN输入端口和BISR_IN输入端口。 N组数据端口中的每一个包括（1）用于连接到相应存储器实例的输入的PHY_IN输出端口; （2）用于连接到相应存储器实例的输出的PHY_OUT输入端口; （3）用于向相应的存储器实例发送信号的LOG_IN输入端口; 和（4）用于从相应的存储器实例接收信号的LOG_OUT输出端口。 N BISR_SUBMOD模块中的每一个包括触发器，第一多路复用器和第二复用器。 CLK_IN输入端口连接到存储器BISR控制器的所有N个触发器的时钟输入。 BISR_IN输入端口连接到第一触发器的数据输入，第K触发器的输出连接到第（K + 1）个触发器的输入，K = 1,2。。。，N-1。当N个存储器实例中的至少一个存在缺陷时，存储器BISR控制器可以重新配置N个存储器实例之间的连接以使用其他存储器实例而不是缺陷存储器实例。

10. 发明授权

US07216278B2 Method and BIST architecture for fast memory testing in platform-based integrated circuit 有权
标题翻译：方法和BIST架构，用于基于平台的集成电路中的快速内存测试
公开(公告)号：US07216278B2
公开(公告)日：2007-05-08
申请号：US10999493
申请日：2004-11-30
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/26 , G11C2029/2602
摘要： The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
摘要翻译：本发明提供了一种用于基于平台的集成电路中的快速存储器测试的方法和BIST架构。该方法可以包括以下步骤。启动Mem-BIST控制器发送器，使用确定性和无条件测试算法为平台中的存储器生成输入信号。输入信号被第一组管道延迟了n个时钟周期。延迟的输入信号由存储器接收，并且由存储器产生输出信号。输出信号被第二个流水线延迟了m个时钟周期。启动Mem-BIST控制器接收器以接收延迟的输出信号进行比较。

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