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1. 发明授权

US06548874B1 Higher voltage transistors for sub micron CMOS processes 有权
标题翻译：用于亚微米CMOS工艺的高压晶体管
公开(公告)号：US06548874B1
公开(公告)日：2003-04-15
申请号：US09669391
申请日：2000-09-26
申请人： Alec Morton , Taylor Efland , Chin-yu Tsai , Jozef C. Mitros , Dan M. Mosher , Sam Shichijo , Keith Kunz
发明人： Alec Morton , Taylor Efland , Chin-yu Tsai , Jozef C. Mitros , Dan M. Mosher , Sam Shichijo , Keith Kunz
IPC分类号： H01L2976
CPC分类号： H01L27/092 , H01L29/0653 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.
摘要翻译：用于亚微米CMOS工艺的集成电路漏极延伸晶体管。在硅衬底（10）中的CMOS n阱区（80）和CMOS p阱区（70）上形成晶体管栅极（40）。晶体管源极区域（50），（140）和漏极区域（55），（145）形成在各种CMOS阱区域中以形成漏极延伸晶体管，其中CMOS阱区域（70），（80）用作漏极延伸晶体管的区域。

2. 发明授权

US06483149B1 LDMOS device with self-aligned resurf region and method of fabrication 失效
标题翻译：具有自对准复制区域的LDMOS器件和制造方法
公开(公告)号：US06483149B1
公开(公告)日：2002-11-19
申请号：US08856498
申请日：1997-05-14
申请人： Dan M. Mosher , Taylor R. Efland
发明人： Dan M. Mosher , Taylor R. Efland
IPC分类号： H01L27092
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/42368 , H01L29/66659
摘要： A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.
摘要翻译： RESURF LDMOS晶体管（64）包括与LOCOS场氧化物区域（44）自对准的RESURF区域（42）。自对准通过消除与几何不对准和工艺公差变化相关的劣化产生稳定的击穿电压BVdss。

3. 发明授权

US5256582A Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate 失效
标题翻译：在相同的集成电路基板上形成具有功率和逻辑结构的互补双极和MOS晶体管的方法
公开(公告)号：US5256582A
公开(公告)日：1993-10-26
申请号：US800869
申请日：1991-11-27
申请人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton , Bob Todd
发明人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton , Bob Todd
IPC分类号： H01L27/06 , H01L21/00 , H01L21/02 , H01L21/22 , H01L21/26
CPC分类号： H01L27/0623 , Y10S148/009
摘要： The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known. For example, the present integrated circuit chip, uses bipolar power transistors instead of vertical DMOS power transistors for power applications. The bipolar power transistors are more rugged and have higher power handling capabilities than DMOS devices. Thus the bipolar transistors can be used for any out-stage configuration, including low side, high side, half bridge and full bridge output circuits. The versatility of the present process flow allows the fabrication of MOSFET, BiMOS, BiCMOS, and bipolar technology either discretely or with high power or low power NPN or PNP devices.
摘要翻译：本发明涉及一种制造半导体集成器件的方法，更具体地说，涉及一种具有NPN和PNP功率的半导体集成器件以及与互补MOS和DMOS器件相结合的逻辑器件。本发明是用于制造高功率/逻辑互补双极/ MOS / DMOS（CBiCMOS）集成电路的多轴工艺。用于制造新型集成电路的工艺步骤组合在具有互补MOSGVm器件和DMOSFET器件的相同衬底互补大功率逻辑/模拟双极晶体管上。本发明在单个工艺流程中优化这些不同晶体管的特性。目前的高功率/逻辑CBiCMOS多外延工艺导致了与先前已知的现有技术工艺和结构相比具有不同技术优点的器件结构。例如，本集成电路芯片采用双极型功率晶体管代替用于功率应用的垂直DMOS功率晶体管。双极功率晶体管比DMOS器件更加坚固耐用，具有更高的功率处理能力。因此，双极晶体管可用于任何外置配置，包括低端，高端，半桥和全桥输出电路。本工艺流程的多功能性允许离散地或与高功率或低功率NPN或PNP器件制造MOSFET，BiMOS，BiCMOS和双极技术。

4. 发明授权

US06624487B1 Drain-extended MOS ESD protection structure 有权
标题翻译：漏极扩展MOS静电保护结构
公开(公告)号：US06624487B1
公开(公告)日：2003-09-23
申请号：US10163712
申请日：2002-06-05
申请人： Keith E. Kunz , Charvaka Duvvury , Dan M. Mosher
发明人： Keith E. Kunz , Charvaka Duvvury , Dan M. Mosher
IPC分类号： H01L2972
CPC分类号： H01L27/0266
摘要： A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed. An ESD event received at the terminal (IN) is thus coupled to the gate of the transistors (32, 34), causing conduction to the substrate (40) via the guard ring (50), and turning on a parasitic bipolar transistor at the other transistor (34), safely conducting the ESD current. One alternative structure (30′) includes a junction capacitor (65) coupled between the terminal (IN) and the gates of the transistors (32, 34) to improve the coupling. Another alternative structure (30″) includes a clamping diode (92) that also presents a parasitic bipolar transistor (95) enhancing the current conducted to the substrate (40).
摘要翻译：公开了一种用于在端子（IN）处安全地从静电放电（ESD）传导电荷的保护结构（30; 30'; 30“）。保护结构（30; 30'; 30“）包括一对漏极延伸的金属氧化物半导体（MOS）晶体管（32,34）。在泵浦晶体管（32）中，栅电极（45）与布置有漏极（44）的阱（42）的一部分重叠，以提供有效的栅 - 漏电容。晶体管（32,34）的漏极连接在一起并连接到端子（IN），而晶体管（32,34）的栅极连接在一起。一个晶体管（32）的源极连接到与其他晶体管（34）的沟道区域设置在其中的衬底（40）相同的导电类型的保护环（50）。因此，在端子（IN）处接收到的ESD事件被耦合到晶体管（32,34）的栅极，从而经由保护环（50）导通到衬底（40），并且在第其他晶体管（34），安全地传导ESD电流。一个替代结构（30'）包括耦合在端子（IN）和晶体管（32,34）的栅极之间的结电容器（65），以改善耦合。另一替代结构（30“）包括钳位二极管（92），其还具有增强传导到衬底（40）的电流的寄生双极晶体管（95）。

5. 发明授权

US06521946B2 Electrostatic discharge resistant extended drain metal oxide semiconductor transistor 有权
公开(公告)号：US06521946B2
公开(公告)日：2003-02-18
申请号：US09998620
申请日：2001-11-30
申请人： Dan M. Mosher
发明人： Dan M. Mosher
IPC分类号： H01L2976
CPC分类号： H01L29/0653 , H01L29/7834 , H01L29/7835
摘要： A semiconductor device comprising a first transistor (40) and a second transistor (100), both formed in a semiconductor substrate (50). The first transistor comprises a gate conductor (56) and a gate insulator (54) separating the gate conductor from a semiconductor material and defining a channel area (66) in the semiconductor material opposite from the gate conductor. The first transistor further comprises a source (S2) comprising a first doped region (581) of a first conductivity type and adjacent the channel area. Further, the first transistor comprises a drain (D2). The drain comprises a first well (641) adjacent the channel area and having a first concentration of the first conductivity type and a first doped region portion and a second doped portion (68). The first doped portion has a second concentration of the first conductivity type. The second concentration is greater than the first concentration and the first doped region portion has a common interface with the first well. The second doped region portion has the second concentration of the first conductivity type, wherein the second doped region portion has no common interface with the first well and is not adjacent the channel area. The second transistor (100) comprises a second well (642) formed using the same implant step as the first well and thereby having the first concentration of the first conductivity type. The second transistor further comprises a first source/drain (1101) and a second source/drain (1102), both comprising a second conductivity type complementary of the first conductivity type and formed within the second well.

6. 发明授权

US5153697A Integrated circuit that combines multi-epitaxial power transistors with logic/analog devices, and a process to produce same 失效
标题翻译：将多外延功率晶体管与逻辑/模拟器件相结合的集成电路，以及生产相同的工艺
公开(公告)号：US5153697A
公开(公告)日：1992-10-06
申请号：US695821
申请日：1991-05-06
申请人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton
发明人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton
IPC分类号： H01L21/74 , H01L21/8222 , H01L21/8226 , H01L21/8234 , H01L21/8248 , H01L21/8249
CPC分类号： H01L21/8222 , H01L21/74 , H01L21/8226 , H01L21/8234 , H01L21/8248 , H01L21/8249
摘要： An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.
摘要翻译：在基板上具有第一N型外延层的N型半导体晶片上形成集成电路，在第一N型外延层上形成P型外延层，在P型上形成第二N型外延层型外延层。还存在将P型外延区域和第二N型外延区域的表面分离成外延槽区域以形成双极和CMOS器件的多组P型隔离区，其组合高功率，低功率，逻辑，开关，模拟，高电流，低电流，数字和线性双极晶体管以及CMOS晶体管。将不同类型设备的特性组合成单个流程。

7. 发明授权

US07888196B2 Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom 有权
标题翻译：包括具有多个栅介质厚度的工艺和其集成电路的沟槽隔离
公开(公告)号：US07888196B2
公开(公告)日：2011-02-15
申请号：US12345072
申请日：2008-12-29
申请人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
发明人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L21/76229 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness
摘要翻译：一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管，其中所述第一厚度<所述第二厚度。提供具有半导体表面的衬底。具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。在包括第二区域的半导体表面上形成硬掩模层。通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。然后完成第一和第二区域中的MOS晶体管的制造。

8. 发明授权

US06211552B1 Resurf LDMOS device with deep drain region 有权
标题翻译：具有深漏区的LDMOS器件
公开(公告)号：US06211552B1
公开(公告)日：2001-04-03
申请号：US09320953
申请日：1999-05-27
申请人： Taylor R. Efland , Sameer Pendharkar , Dan M. Mosher , Peter Chia-cu Mei
发明人： Taylor R. Efland , Sameer Pendharkar , Dan M. Mosher , Peter Chia-cu Mei
IPC分类号： H01L2978
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/66659 , H01L29/7835
摘要： A RESURF LDMOS transistor (32) has a drain region including a first region (24) and a deep drain buffer region (34) surrounding the first region. The first region is more heavily doped than the deep drain buffer region. The deep drain buffer region improves the robustness of the transistor.
摘要翻译： RESURF LDMOS晶体管（32）具有包括围绕第一区域的第一区域（24）和深漏极缓冲区域（34）的漏极区域。第一区域比深漏极缓冲区域更重掺杂。深漏极缓冲区域提高了晶体管的鲁棒性。

9. 发明授权

US5181095A Complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate 失效
标题翻译：在同一集成电路基板上具有功率和逻辑结构的互补双极和MOS晶体管
公开(公告)号：US5181095A
公开(公告)日：1993-01-19
申请号：US688196
申请日：1991-04-19
申请人： Dan M. Mosher , Larry Latham , Bob Todd , Cornelia H. Blanton , Joe R. Trogolo , David R. Cotton
发明人： Dan M. Mosher , Larry Latham , Bob Todd , Cornelia H. Blanton , Joe R. Trogolo , David R. Cotton
IPC分类号： H01L27/06
CPC分类号： H01L27/0623
摘要： An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.
摘要翻译：在衬底上的第一N型外延层的集成电路器件，在第一外延层上的第二P型外延层和在第二外延层上的第三N型外延层，具有P型埋地区域，其形成在所述衬底的一部分中，所述接地区域在第一槽区域中从所述衬底延伸到所述第三外延层并且延伸穿过所述第一和第二外延层。功率双极晶体管形成在第一槽区中。从第三外延层的表面延伸到P接地区的P隔离区将双极晶体管与其中形成N和P沟道MOSFET的同一衬底上的其它槽区分离。

10. 发明申请

US20100163998A1 TRENCH ISOLATION COMPRISING PROCESS HAVING MULTIPLE GATE DIELECTRIC THICKNESSES AND INTEGRATED CIRCUITS THEREFROM 有权
标题翻译：具有多个栅极介质厚度的封装隔离工艺及其集成电路
公开(公告)号：US20100163998A1
公开(公告)日：2010-07-01
申请号：US12345072
申请日：2008-12-29
申请人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
发明人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L21/823462 , H01L21/76229 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness
摘要翻译：一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管，其中所述第一厚度<所述第二厚度。提供具有半导体表面的衬底。具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。在包括第二区域的半导体表面上形成硬掩模层。通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。然后完成第一和第二区域中的MOS晶体管的制造。

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