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1. 发明申请

US20130130490A1 COMBINATORIAL APPROACH FOR SCREENING OF ALD FILM STACKS 失效
标题翻译： ALD膜片筛选的组合方法
公开(公告)号：US20130130490A1
公开(公告)日：2013-05-23
申请号：US13302730
申请日：2011-11-22
申请人： Albert Lee , Tony P. Chiang , Jason Wright
发明人： Albert Lee , Tony P. Chiang , Jason Wright
IPC分类号： H01L21/28
CPC分类号： H01L21/28562 , C23C16/04 , C23C16/45525 , H01L21/28158 , H01L21/68771 , H01L28/40 , H01L28/60 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1616
摘要： In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
摘要翻译：在本发明的一些实施例中，描述了使用一个或多个小型喷头装置以局部隔离，组合方式在小斑点上使用CVD，PECVD，ALD或PEALD沉积材料的方法。小型喷头可配置在更大的组合喷淋头内，以允许以组合方式沉积多层胶片堆叠。

2. 发明授权

US08609519B2 Combinatorial approach for screening of ALD film stacks 失效
标题翻译：组合方法用于筛选ALD膜堆叠
公开(公告)号：US08609519B2
公开(公告)日：2013-12-17
申请号：US13302730
申请日：2011-11-22
申请人： Albert Lee , Tony P. Chiang , Jason Wright
发明人： Albert Lee , Tony P. Chiang , Jason Wright
IPC分类号： H01L21/00 , H01L21/31 , H01L21/469 , H01L21/20 , H01L21/205 , H01L21/365
CPC分类号： H01L21/28562 , C23C16/04 , C23C16/45525 , H01L21/28158 , H01L21/68771 , H01L28/40 , H01L28/60 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1616
摘要： In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
摘要翻译：在本发明的一些实施例中，描述了使用一个或多个小型喷头装置以局部隔离，组合方式在小斑点上使用CVD，PECVD，ALD或PEALD沉积材料的方法。小型喷头可配置在更大的组合喷淋头内，以允许以组合方式沉积多层胶片堆叠。

3. 发明申请

US20130152857A1 Substrate Processing Fluid Delivery System and Method 审中-公开
标题翻译：基板加工流体输送系统和方法
公开(公告)号：US20130152857A1
公开(公告)日：2013-06-20
申请号：US13327597
申请日：2011-12-15
申请人： Jason Wright , Tony P. Chiang
发明人： Jason Wright , Tony P. Chiang
IPC分类号： C23C16/455 , F15D1/00
CPC分类号： C23C16/4482 , Y10T137/0318 , Y10T137/5283
摘要： Embodiments provided herein describe substrate processing fluid delivery systems and methods. The substrate processing fluid delivery systems include a flow regulator. A fluid conduit assembly is coupled to the flow regulator and a processing chamber of a substrate processing apparatus. A plurality of processing fluid containers is coupled to the fluid conduit assembly. A plurality of valves is coupled to the fluid conduit assembly. The plurality of valves are configurable to selectively place each of the plurality of processing fluid containers in fluid communication with only the flow regulator or the processing chamber of the substrate processing apparatus through the fluid conduit assembly.
摘要翻译：本文提供的实施方案描述了基底处理流体递送系统和方法。基板处理流体输送系统包括流量调节器。流体导管组件联接到流量调节器和衬底处理装置的处理室。多个处理流体容器联接到流体导管组件。多个阀联接到流体导管组件。多个阀可配置成选择性地将多个处理流体容器中的每一个通过流体导管组件与基板处理装置的流量调节器或处理室流体连通。

4. 发明申请

US20140080282A1 Leakage reduction in DRAM MIM capacitors 有权
公开(公告)号：US20140080282A1
公开(公告)日：2014-03-20
申请号：US13621910
申请日：2012-09-18
申请人： Tony P. Chiang , Wim Y. Deweerd , Sandra G. Malhotra
发明人： Tony P. Chiang , Wim Y. Deweerd , Sandra G. Malhotra
IPC分类号： H01L21/02
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

5. 发明授权

US08551809B2 Reduction of forming voltage in semiconductor devices 有权
标题翻译：降低半导体器件中的形成电压
公开(公告)号：US08551809B2
公开(公告)日：2013-10-08
申请号：US12391784
申请日：2009-02-24
申请人： Pragati Kumar , Yun Wang , Prashant Phatak , Tony P. Chiang
发明人： Pragati Kumar , Yun Wang , Prashant Phatak , Tony P. Chiang
IPC分类号： H01L47/00 , H01L29/06 , H01L21/00 , H01L21/16
CPC分类号： H01L45/146 , G11C13/0002 , G11C2013/0083 , G11C2213/51 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/1625 , H01L45/1641
摘要： A nonvolatile memory device and methods of manufacturing the same has one electrode with a higher work function and a second electrode with a lower work function. The nonvolatile memory device further comprises one or more resistive random access memory (RRAM) cells. The RRAM cells comprise a semiconductor layer with a bandgap of at least four electron volts and a barrier layer between the semiconductor layer and one of the electrodes.
摘要翻译：非易失性存储器件及其制造方法具有一个具有较高功函数的电极和具有较低功函数的第二电极。非易失性存储器件还包括一个或多个电阻随机存取存储器（RRAM）单元。 RRAM单元包括具有至少四个电子伏特的带隙的半导体层和在半导体层和电极之一之间的阻挡层。

6. 发明授权

US08389419B2 Combinatorial plasma enhanced deposition techniques 失效
公开(公告)号：US08389419B2
公开(公告)日：2013-03-05
申请号：US13311926
申请日：2011-12-06
申请人： Sunil Shanker , Tony P. Chiang
发明人： Sunil Shanker , Tony P. Chiang
IPC分类号： H01L21/31
CPC分类号： C23C16/047 , C23C16/04 , C23C16/45536 , C23C16/45551 , C23C16/45565 , C23C16/45574 , C23C16/45591 , C23C16/4583 , C23C16/46 , C23C16/50 , C23C16/5096 , C23C16/52 , H01J37/32357 , H01J37/32366
摘要： Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

7. 发明授权

US08298837B2 System and method for increasing productivity of organic light emitting diode material screening 有权
标题翻译：提高有机发光二极管材料筛选生产率的系统和方法
公开(公告)号：US08298837B2
公开(公告)日：2012-10-30
申请号：US13072083
申请日：2011-03-25
申请人： Yun Wang , Tony P. Chiang , Chi-I Lang
发明人： Yun Wang , Tony P. Chiang , Chi-I Lang
IPC分类号： H01L21/00
CPC分类号： H01L51/0031 , H01L51/56
摘要： A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.
摘要翻译：提高OLED材料筛选的生产率的系统和方法包括提供包括有机半导体的衬底，通过组合地改变与衬底上的OLED器件生产相关的参数来在衬底上处理区域，对处理的区域进行第一表征测试所述衬底产生第一结果，基于所述第一表征测试的第一结果，通过改变与所述衬底上的OLED器件生产相关联的参数，以组合方式处理所述衬底上的区域，对所述衬底上的所述处理区域进行第二特性测试衬底以产生第二结果，以及基于第二结果确定衬底是否满足预定质量阈值。

8. 发明申请

US20120119768A1 Method and System of Improved Reliability Testing 有权
标题翻译：改进可靠性测试方法与系统
公开(公告)号：US20120119768A1
公开(公告)日：2012-05-17
申请号：US12948257
申请日：2010-11-17
申请人： Yun Wang , Tony P. Chiang , Ryan Clarke , Chi-I Lang , Yoram Schwarz
发明人： Yun Wang , Tony P. Chiang , Ryan Clarke , Chi-I Lang , Yoram Schwarz
IPC分类号： G01R31/3187 , H01L21/66
CPC分类号： H01L22/14
摘要： A method and system of improved reliability testing includes providing a first substrate and a second substrate, each substrate comprising only a first metallization layer; processing regions on a first substrate by combinatorially varying at least one of materials, unit processes, and process sequences; performing a first reliability test on the processed regions on the first substrate to generate first results; processing regions on a second substrate in a combinatorial manner by varying at least one of materials, unit processes, and process sequences based on the first results of the first reliability test; performing a second reliability test on the processed regions on the second substrate to generate second results; and determining whether the first substrate and the second substrate meet a predetermined quality threshold based on the second results.
摘要翻译：改进的可靠性测试的方法和系统包括提供第一衬底和第二衬底，每个衬底仅包括第一金属化层; 通过组合地改变材料，单元过程和工艺顺序中的至少一个来处理第一衬底上的处理区域; 对所述第一基板上的所述经处理区域进行第一可靠性测试以产生第一结果; 基于第一可靠性测试的第一结果，通过改变材料，单元过程和过程序列中的至少一个来以组合的方式处理第二基板上的区域; 对所述第二基板上的所述经处理区域进行第二可靠性测试以产生第二结果; 以及基于所述第二结果来确定所述第一基板和所述第二基板是否满足预定质量阈值。

9. 发明授权

US08084400B2 Methods for discretized processing and process sequence integration of regions of a substrate 有权
标题翻译：离散化处理方法和基板区域的工艺顺序整合
公开(公告)号：US08084400B2
公开(公告)日：2011-12-27
申请号：US11352077
申请日：2006-02-10
申请人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
发明人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
IPC分类号： C40B50/00
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

10. 发明授权

US08067340B2 Methods for discretized processing and process sequence integration of regions of a substrate 有权
公开(公告)号：US08067340B2
公开(公告)日：2011-11-29
申请号：US12029379
申请日：2008-02-11
申请人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
发明人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
IPC分类号： C40B50/00
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

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