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1. 发明申请

US20090150722A1 Recovering from errors in streaming dsp applications 有权
标题翻译：从流dsp应用程序的错误中恢复
公开(公告)号：US20090150722A1
公开(公告)日：2009-06-11
申请号：US12292944
申请日：2008-12-01
申请人： Alastair David Reid , Daryl Wayne Bradley
发明人： Alastair David Reid , Daryl Wayne Bradley
IPC分类号： G06F11/07
CPC分类号： H04L1/0047 , G06F11/0757 , G06F11/1008 , H04L1/0054 , H04L1/0061
摘要： A data processing system is provided in which processing circuitry performs at least one of a series of data processing operations in dependence upon a set of data values and control circuitry controls execution of the data processing operations. Control path error detection circuitry is provided for detecting a control path error associated with an error in operation of the control circuitry and data path error handling circuitry is arranged to handle recovery from errors in the data values. The control path error detection circuitry is configured to cause the data path error handling circuitry to perform recovery from detected control path errors enabling the series of data processing operations to continue despite the occurrence of the control path error. An associated method and computer program product are also provided.
摘要翻译：提供了一种数据处理系统，其中处理电路根据一组数据值执行一系列数据处理操作中的至少一个，控制电路控制数据处理操作的执行。提供控制路径错误检测电路用于检测与控制电路的操作中的错误相关联的控制路径错误，并且数据路径错误处理电路被设置为处理从数据值中的错误中恢复。控制路径错误检测电路被配置为使得数据路径错误处理电路从检测到的控制路径错误执行恢复，使得一系列数据处理操作能够继续，尽管出现控制路径错误。还提供了相关联的方法和计算机程序产品。

2. 发明授权

US08020039B2 Recovering from errors in streaming DSP applications 有权
标题翻译：从流式DSP应用程序的错误中恢复
公开(公告)号：US08020039B2
公开(公告)日：2011-09-13
申请号：US12292944
申请日：2008-12-01
申请人： Alastair David Reid , Daryl Wayne Bradley
发明人： Alastair David Reid , Daryl Wayne Bradley
IPC分类号： G06F11/00
CPC分类号： H04L1/0047 , G06F11/0757 , G06F11/1008 , H04L1/0054 , H04L1/0061
摘要： A data processing system is provided in which processing circuitry performs at least one of a series of data processing operations in dependence upon a set of data values and control circuitry controls execution of the data processing operations. Control path error detection circuitry is provided for detecting a control path error associated with an error in operation of the control circuitry and data path error handling circuitry is arranged to handle recovery from errors in the data values. The control path error detection circuitry is configured to cause the data path error handling circuitry to perform recovery from detected control path errors enabling the series of data processing operations to continue despite the occurrence of the control path error. An associated method and computer program product are also provided.
摘要翻译：提供了一种数据处理系统，其中处理电路根据一组数据值执行一系列数据处理操作中的至少一个，控制电路控制数据处理操作的执行。提供控制路径错误检测电路用于检测与控制电路的操作中的错误相关联的控制路径错误，并且数据路径错误处理电路被设置为处理从数据值中的错误中恢复。控制路径错误检测电路被配置为使得数据路径错误处理电路从检测到的控制路径错误执行恢复，使得一系列数据处理操作能够继续，尽管出现控制路径错误。还提供了相关联的方法和计算机程序产品。

3. 发明授权

US07325168B2 Trace data source identification within a trace data stream 有权
标题翻译：跟踪数据流中的数据源标识
公开(公告)号：US07325168B2
公开(公告)日：2008-01-29
申请号：US10715394
申请日：2003-11-19
申请人： Daryl Wayne Bradley , Sheldon James Woodhouse , Andrew Brookfield Swaine
发明人： Daryl Wayne Bradley , Sheldon James Woodhouse , Andrew Brookfield Swaine
IPC分类号： G06F11/00
CPC分类号： G06F11/348 , G06F11/3476
摘要： A trace data formatter 30 assembles trace data frames 50. These trace data frames 50 include bytes which may either serve to carry a trace data source identifier ID or trace data. A system being traced has multiple trace data sources 12, 14, 16, 18 and when the trace data source which is generating the current trace data stream changes then a trace data source identifier ID is inserted within the trace data stream.
摘要翻译：跟踪数据格式器30组装跟踪数据帧50。这些跟踪数据帧50包括可用于携带跟踪数据源标识符ID或跟踪数据的字节。正在跟踪的系统具有多个跟踪数据源12,14,16,18，并且当生成当前跟踪数据流的跟踪数据源改变时，跟踪数据源标识符ID被插入跟踪数据流内。

4. 发明申请

US20090292977A1 Error Detecting and Correcting Mechanism for a Register File 有权
标题翻译：寄存器文件的错误检测和校正机制
公开(公告)号：US20090292977A1
公开(公告)日：2009-11-26
申请号：US12226108
申请日：2006-08-15
申请人： Daryl Wayne Bradley , Jason Andrew Blome , Scott Mahlke
发明人： Daryl Wayne Bradley , Jason Andrew Blome , Scott Mahlke
IPC分类号： H03M13/09 , G06F12/02 , G06F11/10
CPC分类号： G06F11/167 , G06F11/1004
摘要： A data processing system includes a register file (2) having a plurality of registers storing respective register data values and an associated register value cache (12) having a plurality of storage locations (14) storing corresponding cache data values. There are fewer cache data values than registers. When a register is to be read, both the register data value and, if present, a cache data value from a corresponding storage location (14) within the register value cache (12) are read and compared by a comparator (18). This generates a match signal which indicates if the data values do not match that one of the data values is in error. The match signal stalls the processing and a CRC code initially stored with the cache data value and recalculated based upon the read cache data value are compared to determine whether or not the cache data value has changed since it was stored. If the cache data value has not changed, then it is correct and is output instead of the register data value. Alternatively, if the cache data value has changed, then the register data value is output.
摘要翻译：数据处理系统包括具有存储相应寄存器数据值的多个寄存器的寄存器文件（2）和具有存储对应高速缓存数据值的多个存储位置（14）的关联寄存器值缓存（12）。缓存数据值比寄存器少。当要读取寄存器时，寄存器数据值和寄存器值高速缓冲存储器（12）中对应的存储位置（14）的高速缓存数据值（如果存在）都被比较器（18）比较。这产生一个匹配信号，它指示数据值是否与数据值之一不符。匹配信号使处理停止，并且比较最初存储有高速缓存数据值并基于读取的高速缓存数据值重新计算的CRC码，以确定高速缓存数据值是否已经被存储以来已经改变。如果缓存数据值没有改变，那么它是正确的并且是输出而不是寄存器数据值。或者，如果缓存数据值已经改变，则输出寄存器数据值。

5. 发明授权

US07191293B2 Recovering pending trace data within a data processing system 有权
标题翻译：恢复数据处理系统中的待处理跟踪数据
公开(公告)号：US07191293B2
公开(公告)日：2007-03-13
申请号：US10801137
申请日：2004-03-16
申请人： Daryl Wayne Bradley , Andrew Brookfield Swaine , Sheldon James Woodhouse , John Michael Horley
发明人： Daryl Wayne Bradley , Andrew Brookfield Swaine , Sheldon James Woodhouse , John Michael Horley
IPC分类号： G06F12/06 , G06F9/44
CPC分类号： G06F11/3476
摘要： A trace data system is provided in which flush request signals are generated and passed to trace data sources to trigger them to output any buffered trace data they are storing which was generated prior to the flush request being signalled. When the trace data has been flushed from these trace data sources, they signal this by generating a flush complete signal. The flushing of trace data may advantageously be performed prior to a power-down operation and using a trace bus bridge.
摘要翻译：提供跟踪数据系统，其中生成刷新请求信号并将其传递到跟踪数据源，以触发它们输出它们正在存储的任何缓冲的跟踪数据，该数据是在发送刷新请求之前生成的。当跟踪数据从这些跟踪数据源中刷新时，它们会通过生成一个完整的完成信号来发出信号。跟踪数据的刷新可以有利地在掉电操作之前和使用跟踪总线桥处执行。

6. 发明授权

US08468394B2 Method of tracing selected activities within a data processing system by tagging selected items and tracing the tagged items 有权
标题翻译：通过标记所选项目和跟踪标记的项目来跟踪数据处理系统中所选活动的方法
公开(公告)号：US08468394B2
公开(公告)日：2013-06-18
申请号：US12224874
申请日：2006-03-09
申请人： Daryl Wayne Bradley , John Michael Horley , Sheldon James Woodhouse
发明人： Daryl Wayne Bradley , John Michael Horley , Sheldon James Woodhouse
IPC分类号： G06F11/00 , G06F11/34
CPC分类号： G06F11/364
摘要： A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one item, said at least one item comprising an activity to be monitored; provide said at least one selected item with tag data identifying said at least one item as an item to be monitored; and said trace logic being operable to: detect tagged items processed by said at least one device; and output trace information relating to at least some of said detected tagged items.
摘要翻译：公开了一种数据处理设备，所述数据处理设备包括多个设备，与所述多个设备中的至少一个相关联的跟踪逻辑以及与所述多个设备中的至少一个相关联的标记逻辑，所述标记逻辑可操作为：选择至少一个项目，所述至少一个项目包括要监视的活动; 向所述至少一个所选项目提供标识所述至少一个项目的标签数据作为待监视的项目; 并且所述跟踪逻辑可操作用于：检测由所述至少一个设备处理的标记的项目; 并且输出与至少一些所述检测到的标记物品相关的跟踪信息。

7. 发明申请

US20090177928A1 Apparatus, Method and Computer Program Product for Generating Trace Data 有权
标题翻译：用于生成跟踪数据的装置，方法和计算机程序产品
公开(公告)号：US20090177928A1
公开(公告)日：2009-07-09
申请号：US12224874
申请日：2006-03-09
申请人： Daryl Wayne Bradley , John Michael Horley , Sheldon James Woodhouse
发明人： Daryl Wayne Bradley , John Michael Horley , Sheldon James Woodhouse
IPC分类号： G06F11/34
CPC分类号： G06F11/364
摘要： A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one item, said at least one item comprising an activity to be monitored; provide said at least one selected item with tag data identifying said at least one item as an item to be monitored; and said trace logic being operable to: detect tagged items processed by said at least one device; and output trace information relating to at least some of said detected tagged items.
摘要翻译：公开了一种数据处理设备，所述数据处理设备包括多个设备，与所述多个设备中的至少一个相关联的跟踪逻辑，以及与所述多个设备中的至少一个相关联的标记逻辑，所述标记逻辑可操作为：选择至少一个项目，所述至少一个项目包括要监视的活动; 向所述至少一个所选项目提供标识所述至少一个项目的标签数据作为待监视的项目; 并且所述跟踪逻辑可操作用于：检测由所述至少一个设备处理的标记的项目; 并且输出与至少一些所述检测到的标记物品相关的跟踪信息。

8. 发明申请

US20090049331A1 Error propagation control within integrated circuits 有权
标题翻译：集成电路内的误差传播控制
公开(公告)号：US20090049331A1
公开(公告)日：2009-02-19
申请号：US11887106
申请日：2005-10-03
申请人： Jason Andrew Blome , Krisztian Flautner , Daryl Wayne Bradley
发明人： Jason Andrew Blome , Krisztian Flautner , Daryl Wayne Bradley
IPC分类号： G06F11/20
CPC分类号： G06F11/261 , G06F17/5045 , Y02T10/82
摘要： A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.
摘要翻译：选择错误检测电路应放置在集成电路中的方法，使用注入到测试设计中的错误的参考和测试设计的仿真，然后扇出对这些注入错误进行的分析，以识别误差传播特性。因此，可以识别传播错误很可能表现自身或者保护关键体系结构状态或哪个保护状态没有被其他方式保护的寄存器，从而实现错误检测机制的有效部署。在集成电路内，根据检测到的集成电路的当前状态，来自非活动电路元件的输出信号可能经受隔离门控。因此，出现软错误的无效电路元件具有不适当的输出信号，从而不能到达集成电路的其余部分，从而减少错误的操作。

9. 发明授权

US07149933B2 Data processing system trace bus 有权
标题翻译：数据处理系统跟踪总线
公开(公告)号：US07149933B2
公开(公告)日：2006-12-12
申请号：US10635920
申请日：2003-08-07
申请人： Andrew Brookfield Swaine , Daryl Wayne Bradley , Sheldon James Woodhouse
发明人： Andrew Brookfield Swaine , Daryl Wayne Bradley , Sheldon James Woodhouse
IPC分类号： G06F11/00
CPC分类号： G06F11/348 , G06F11/3476
摘要： An integrated circuit 2 is provided with multiple sources 12, 14, 16, 18 of trace data streams that are input via respective dedicated trace buses 20, 24 to a trace data stream combiner 22, 26. The trace data bus has trace data signal lines ATDATA for carrying trace data signals and trace source identifying signal lines ATID for carrying trace source identifying signals. A trace data stream replicator 28 may be used to replicate a single trace data stream such that the resulting multiple trace data streams may be subject to different post-replication processing/filtering as desired.
摘要翻译：集成电路2具有经由各自的专用跟踪总线20,24输入到跟踪数据流组合器22,26的多个源12,14,16,18的跟踪数据流。跟踪数据总线具有用于承载跟踪数据信号的跟踪数据信号线ATDATA和用于承载跟踪源识别信号的跟踪源识别信号线ATID。跟踪数据流复制器28可以用于复制单个跟踪数据流，使得所得到的多个跟踪数据流可以根据需要进行不同的后复制处理/过滤。

10. 发明授权

US07617409B2 System for checking clock-signal correspondence 有权
标题翻译：用于检查时钟信号对应的系统
公开(公告)号：US07617409B2
公开(公告)日：2009-11-10
申请号：US11414551
申请日：2006-05-01
申请人： David Michael Gilday , Daryl Wayne Bradley , Edmond John Simon Ashfield
发明人： David Michael Gilday , Daryl Wayne Bradley , Edmond John Simon Ashfield
IPC分类号： G06F1/04 , G06F1/12 , G06F1/00 , H03K19/00 , H03K10/096
CPC分类号： G06F1/10 , H03K23/52
摘要： A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock. Furthermore the clock-signal comparator is implemented in a hardware description language and integrated in a simulation of the operation of a data processing apparatus to detect timing errors that arise from numerical artifacts of the simulation as well as timing errors that arise from configuration and layout of the circuit elements of the data processing apparatus being simulated.
摘要翻译：提供一种数据处理系统，其具有时钟信号比较器，该时钟信号比较器包括用于接收参考时钟信号的参考输入端口和用于接收相应另外的时钟信号的至少另一输入端口在时钟信号比较器内提供校验逻辑，以在预定时间窗内检查参考时钟信号的时钟沿与另一时钟信号的对应时钟沿之间的对应关系。检查逻辑可操作以在数据处理系统的操作期间检查对应关系。时钟信号比较器可以被提供在集成电路上或作为数据处理装置的一部分，该数据处理装置具有至少两个不同的定时域，例如与相同时钟的两个不同实例相关联的定时域。此外，时钟信号比较器以硬件描述语言实现，并且集成在数据处理装置的操作的仿真中，以检测由仿真的数字伪像产生的定时误差以及由配置和布局引起的定时误差模拟数据处理装置的电路元件。

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