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2. 发明授权

US07617409B2 System for checking clock-signal correspondence 有权
标题翻译：用于检查时钟信号对应的系统
公开(公告)号：US07617409B2
公开(公告)日：2009-11-10
申请号：US11414551
申请日：2006-05-01
申请人： David Michael Gilday , Daryl Wayne Bradley , Edmond John Simon Ashfield
发明人： David Michael Gilday , Daryl Wayne Bradley , Edmond John Simon Ashfield
IPC分类号： G06F1/04 , G06F1/12 , G06F1/00 , H03K19/00 , H03K10/096
CPC分类号： G06F1/10 , H03K23/52
摘要： A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock. Furthermore the clock-signal comparator is implemented in a hardware description language and integrated in a simulation of the operation of a data processing apparatus to detect timing errors that arise from numerical artifacts of the simulation as well as timing errors that arise from configuration and layout of the circuit elements of the data processing apparatus being simulated.
摘要翻译：提供一种数据处理系统，其具有时钟信号比较器，该时钟信号比较器包括用于接收参考时钟信号的参考输入端口和用于接收相应另外的时钟信号的至少另一输入端口在时钟信号比较器内提供校验逻辑，以在预定时间窗内检查参考时钟信号的时钟沿与另一时钟信号的对应时钟沿之间的对应关系。检查逻辑可操作以在数据处理系统的操作期间检查对应关系。时钟信号比较器可以被提供在集成电路上或作为数据处理装置的一部分，该数据处理装置具有至少两个不同的定时域，例如与相同时钟的两个不同实例相关联的定时域。此外，时钟信号比较器以硬件描述语言实现，并且集成在数据处理装置的操作的仿真中，以检测由仿真的数字伪像产生的定时误差以及由配置和布局引起的定时误差模拟数据处理装置的电路元件。

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