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1. 发明授权

US06563727B1 Method and structure for reducing noise effects in content addressable memories 失效
标题翻译：用于减少内容可寻址存储器中的噪声影响的方法和结构
公开(公告)号：US06563727B1
公开(公告)日：2003-05-13
申请号：US10208011
申请日：2002-07-31
申请人： Alan Roth , Hamed Ghassemi
发明人： Alan Roth , Hamed Ghassemi
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A method for reducing the coupling noise in a Content Addressable Memory (CAM), the CAM having a first bitline pair and a second bitline pair, both pairs aligned along a first axis; a first memory cell connected to the first bitline pair and a second memory cell to the second bitline pair; having a first match line and a first word line aligned along a second axis, the first match line and the first word line connecting the first and the second memory cells defining a first row in a first column; having a second row adjacent the first row, the second row comprising a third cell and a fourth cell, the third and fourth cells connecting the first and second bitline pairs and a second word line and a second match line, the method comprising arranging the first memory cell in a first orientation and the second memory cell in a second orientation, wherein the second orientation being a first axis mirror image to the first orientation; segmenting the first and second bitline pairs between the first row and the second row; adding a first twisting structure to the first bitline pair and a second twisting structure to the second bitline pair; arranging the third cell in a third orientation, the third orientation being rotated 180 degrees with respect to the first orientation; and arranging the fourth cell in a fourth orientation, the fourth orientation being rotated 180 degrees with respect to the second orientation.
摘要翻译：一种用于减少内容可寻址存储器（CAM）中的耦合噪声的方法，所述CAM具有沿着第一轴对准的第一位线对和第二位线对; 连接到第一位线对的第一存储器单元和到第二位线对的第二存储器单元; 具有沿着第二轴对准的第一匹配线和第一字线，所述第一匹配线和所述第一字线连接限定第一列中的第一行的所述第一和第二存储器单元; 具有与第一行相邻的第二行，第二行包括第三单元和第四单元，第三单元和第四单元连接第一和第二位线对以及第二字线和第二匹配线，该方法包括将第一行存储单元，并且所述第二存储单元处于第二取向，其中所述第二取向是到所述第一取向的第一轴镜像; 分割第一行和第二行之间的第一和第二位线对; 将第一扭转结构添加到所述第一位线对，将第二扭转结构添加到所述第二位线对; 以第三方向布置第三单元，第三取向相对于第一取向旋转180度; 以及将所述第四单元格设置在第四取向中，所述第四取向相对于所述第二取向旋转180度。

2. 发明授权

US5278464A Using delay to obtain high speed current driver circuit 失效
标题翻译：使用延时获得高速电流驱动电路
公开(公告)号：US5278464A
公开(公告)日：1994-01-11
申请号：US892834
申请日：1992-06-02
申请人： Perry H. Pelley, III , Hamed Ghassemi
发明人： Perry H. Pelley, III , Hamed Ghassemi
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/0136 , H03K19/086
摘要： A current driver circuit (10) sources current to an output node (N4) in response to an input signal (VI) being a logic high. The current driver circuit (10) utilizes a current source (16) which sinks current from the output node (N4) in response to the input signal (VI) switching from a logic high to a logic low. The current source (16) is deactivated for a predetermined time delay after the input signal (Vi) switches from a logic high to a logic low.
摘要翻译：电流驱动器电路（10）响应于逻辑高的输入信号（VI）将电流供给到输出节点（N4）。当前的驱动器电路（10）利用电流源（16），其响应于从逻辑高电平切换到逻辑低电平的输入信号（VI），从电流源输出来自输出节点（N4）的电流。在输入信号（Vi）从逻辑高电平切换到逻辑低电平之后，电流源（16）被停用预定的时间延迟。

3. 发明授权

US06757852B1 Self resetting high speed redundancy circuit and method thereof 有权
标题翻译：自复位高速冗余电路及其方法
公开(公告)号：US06757852B1
公开(公告)日：2004-06-29
申请号：US09610028
申请日：2000-07-05
申请人： Hamed Ghassemi , Dimitris C. Pantelakis , Wai T. Lau
发明人： Hamed Ghassemi , Dimitris C. Pantelakis , Wai T. Lau
IPC分类号： G11C2900
CPC分类号： G11C29/84
摘要： A memory circuit includes a memory structure having sets of redundant columns where each set of redundant columns can replace a column of the memory array that may include a defective cell. Selection of the redundant columns for a memory access is accomplished by performing an address comparison between the address provided to the memory and one or more predetermined values that indicate which portion of the data array each set of redundant columns replaces. Based on this address comparison, a column redundancy select signal is asserted when a set of redundant columns is selected. For a read operation, the column redundancy select signal propagates through redundant column logic select the appropriate data from a particular set of redundant columns. This redundant data that is selected is substituted for data stored in the memory array for the read operation. A de-select feedback signal is generated based on the column redundancy select signal The de-select feedback signal is self resetting by causing the column redundancy select signal to be de-asserted after a time period adequate for the memory operation to complete.
摘要翻译：存储器电路包括具有冗余列集合的存储器结构，其中每组冗余列可以替代可能包括有缺陷单元的存储器阵列的列。用于存储器访问的冗余列的选择通过执行提供给存储器的地址与指示每组冗余列的数据阵列的哪个部分替换的一个或多个预定值之间的地址比较来实现。基于该地址比较，当选择一组冗余列时，列冗余选择信号被断言。对于读取操作，列冗余选择信号通过冗余列逻辑进行传播，从一组特定的冗余列中选择适当的数据。所选择的冗余数据被替换存储在存储器阵列中用于读取操作的数据。基于列冗余选择信号产生去选择反馈信号。通过在足以使存储器操作完成的时间段之后导致列冗余选择信号被解除断言，去选择反馈信号是自复位的。

4. 发明授权

US08611162B2 Circuit for preventing a dummy read in a memory 有权
标题翻译：用于防止在存储器中进行虚拟读取的电路
公开(公告)号：US08611162B2
公开(公告)日：2013-12-17
申请号：US13075768
申请日：2011-03-30
申请人： Hamed Ghassemi , Jogendra C. Sarker
发明人： Hamed Ghassemi , Jogendra C. Sarker
IPC分类号： G11C7/22
CPC分类号： G11C11/412 , G11C11/419
摘要： A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal.
摘要翻译：存储器包括行解码器，列逻辑和具有以行和列排列的多个存储器单元的存储器阵列。多个写入字线耦合到行解码器。多个互补写入字线耦合到行解码器。多个读位线耦合到列逻辑。多个写位线耦合到列逻辑。多个列解码写使能线耦合到列逻辑。多个存储单元中的每个存储单元耦合到相应的写入控制电路。每个写入控制电路包括耦合在列解码写入使能线和存储器单元的存取晶体管之间的传输门。传输门由写入字线信号控制。

5. 发明授权

US5572467A Address comparison in an inteagrated circuit memory having shared read global data lines 失效
标题翻译：具有共享读取全局数据线的积分电路存储器中的地址比较
公开(公告)号：US5572467A
公开(公告)日：1996-11-05
申请号：US426995
申请日：1995-04-24
申请人： Hamed Ghassemi , Perry H. Pelley, III , Scott G. Nogle
发明人： Hamed Ghassemi , Perry H. Pelley, III , Scott G. Nogle
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051
摘要： A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).
摘要翻译：同步集成电路存储器（30）在读写操作期间具有从存储器阵列（32）读取的数据与从数据输入寄存器（40）读取的数据之间共享的读出的全局数据线。比较器/锁存器（50）将新地址与先前地址进行比较，并产生用于选择匹配读出放大器（52）和取消选择常规读出放大器（54）的地址匹配信号。使用比较器/锁存器（50）对每个列地址信号实现相对快速的地址比较和地址匹配信号生成，并且发射器对每个匹配信号求和以提供地址匹配信号。使用发射极相加减少了门延迟的数量，从而允许在可以选择常规读出放大器（54）之前产生地址匹配信号，并允许共享读取的全局数据线，而不增加读取全局数据线的访问时间集成电路存储器（30）。

6. 发明授权

US5502676A Integrated circuit memory with column redundancy having shared read global data lines 失效
标题翻译：具有列冗余的集成电路存储器具有共享读取全局数据线
公开(公告)号：US5502676A
公开(公告)日：1996-03-26
申请号：US426994
申请日：1995-04-24
申请人： Perry H. Pelley, III , Hamed Ghassemi
发明人： Perry H. Pelley, III , Hamed Ghassemi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/84
摘要： An integrated circuit memory (30) having redundancy shares read, global data lines shared between a regular memory array (35) and a plurality of redundant columns (41). Redundant data and regular data are multiplexed onto the read global data lines by emitter summing bipolar transistors of regular sense amplifiers (46) with a redundant multiplexer (83). When a redundant column is used to replace a defective regular column, a match circuit (88) generates a match signal for selecting a redundant multiplexer circuit (84, 85, or 86) and for deselecting a corresponding regular sense amplifier (46). The match circuit (88) includes emitter summing circuits (230, 240) to rapidly generate the match signal.
摘要翻译：具有冗余共享读取的集成电路存储器（30），在常规存储器阵列（35）和多个冗余列（41）之间共享的全局数据线。冗余数据和常规数据通过具有冗余多路复用器（83）的常规读出放大器（46）的发射极相加双极晶体管复用到读取的全局数据线上。当冗余列用于替换有缺陷的常规列时，匹配电路（88）产生用于选择冗余多路复用器电路（84,85或86）并用于取消选择相应的规则读出放大器（46）的匹配信号。匹配电路（88）包括用于快速产生匹配信号的发射极加法电路（230,240）。

7. 发明授权

US07518933B2 Circuit for use in a multiple block memory 有权
标题翻译：用于多块存储器的电路
公开(公告)号：US07518933B2
公开(公告)日：2009-04-14
申请号：US11672279
申请日：2007-02-07
申请人： Hamed Ghassemi , Huy B. Nguyen
发明人： Hamed Ghassemi , Huy B. Nguyen
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G06F12/0893 , G11C7/106 , G11C8/12 , G11C2207/2245
摘要： A portion of a memory may include a first memory block, including a first memory cell coupled to a first memory data line, a second memory block, including a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.
摘要翻译：存储器的一部分可以包括第一存储器块，包括耦合到第一存储器数据线的第一存储器单元，包括耦合到第二存储器数据线的第二存储器单元的第二存储器块，以及具有第一存储器终端和第二终端。存储器的部分还可以包括第一N沟道晶体管，其具有耦合到锁存器的第一端的第一电流电极，具有耦合到第一电源电压的第二电流电极，并且具有耦合到第一个内存数据线。存储器的部分还可以包括第二N沟道晶体管，其具有耦合到锁存器的第一端的第一电流电极，具有耦合到第一电源电压的第二电流电极，并且具有耦合到第一电源电压的控制电极第二存储器数据线。

8. 发明申请

US20080279029A1 LOW VOLTAGE DATA PATH IN MEMORY ARRAY 有权
标题翻译：存储器阵列中的低电压数据路径
公开(公告)号：US20080279029A1
公开(公告)日：2008-11-13
申请号：US11746126
申请日：2007-05-09
申请人： Maciej Bajkowski , Hamed Ghassemi , Huy B. Nguyen
发明人： Maciej Bajkowski , Hamed Ghassemi , Huy B. Nguyen
IPC分类号： G11C5/14
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1069
摘要： A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.
摘要翻译：存储器的数据路径来自存储器的阵列，通过读出放大器，通过NOR门，通过N沟道晶体管，以及通过提供输出的锁存器。读出放大器向NOR门提供互补数据，这些数字向N沟道晶体管提供输出。 NOR门向锁存器提供输出。这具有向一个逆变器的栅极和另一个逆变器的漏极提供输出的影响。附加的P沟道晶体管与锁存器的反相器串联。与漏极接收信号的反相器串联的P沟道晶体管被非门的输出导通，以阻止向提供输入到锁存器的N沟道晶体管的电流流动。电流的阻塞减小了N沟道晶体管必须吸收的电流量。这使得即使在降低的电压下，N沟道晶体管也能充分导通以翻转锁存器的状态。

9. 发明授权

US07450454B1 Low voltage data path in memory array 有权
标题翻译：存储器阵列中的低电压数据通路
公开(公告)号：US07450454B1
公开(公告)日：2008-11-11
申请号：US11746126
申请日：2007-05-09
申请人： Maciej Bajkowski , Hamed Ghassemi , Huy B. Nguyen
发明人： Maciej Bajkowski , Hamed Ghassemi , Huy B. Nguyen
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1069
摘要： A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.
摘要翻译：存储器的数据路径来自存储器的阵列，通过读出放大器，通过NOR门，通过N沟道晶体管，以及通过提供输出的锁存器。读出放大器向NOR门提供互补数据，这些数字向N沟道晶体管提供输出。 NOR门向锁存器提供输出。这具有向一个逆变器的栅极和另一个逆变器的漏极提供输出的影响。附加的P沟道晶体管与锁存器的反相器串联。与漏极接收信号的反相器串联的P沟道晶体管被非门的输出导通，以阻止向提供输入到锁存器的N沟道晶体管的电流流动。电流的阻塞减小了N沟道晶体管必须吸收的电流量。这使得即使在降低的电压下，N沟道晶体管也能充分导通以翻转锁存器的状态。

10. 发明申请

US20080186797A1 CIRCUIT FOR USE IN A MULTIPLE BLOCK MEMORY 有权
标题翻译：用于多个块存储器的电路
公开(公告)号：US20080186797A1
公开(公告)日：2008-08-07
申请号：US11672279
申请日：2007-02-07
申请人： Hamed Ghassemi , Huy B. Nguyen
发明人： Hamed Ghassemi , Huy B. Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G06F12/0893 , G11C7/106 , G11C8/12 , G11C2207/2245
摘要： A portion of a memory may include a first memory block, comprising a first memory cell coupled to a first memory data line, a second memory block, comprising a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.
摘要翻译：存储器的一部分可以包括第一存储器块，其包括耦合到第一存储器数据线的第一存储器单元，第二存储器块，包括耦合到第二存储器数据线的第二存储器单元，以及锁存器，终端和第二终端。存储器的部分还可以包括第一N沟道晶体管，其具有耦合到锁存器的第一端的第一电流电极，具有耦合到第一电源电压的第二电流电极，并且具有耦合到第一个内存数据线。存储器的部分还可以包括第二N沟道晶体管，其具有耦合到锁存器的第一端的第一电流电极，具有耦合到第一电源电压的第二电流电极，并且具有耦合到第一电源电压的控制电极第二存储器数据线。

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