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1. 发明专利

JPS6123356A Apparatus for preventing electrostatic breakdown of semiconductor device 失效
标题翻译：防止半导体器件静电破坏的装置
公开(公告)号：JPS6123356A
公开(公告)日：1986-01-31
申请号：JP14239484
申请日：1984-07-11
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TAKIGAWA AKIRA , HAIJIMA MIKIO , IHARA HIROSHI , WATABE TOMOYUKI , WASHIO KATSUYOSHI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0255
摘要： PURPOSE:To absorb both positive and negative surge pulses by forming an n type buried layer as a protection resistance and using a junction diode composed of the n type region and the p type diffused region. CONSTITUTION:When a forward surge pulse enters the electrode in the input terminal side, a voltage drops due to a resistance while a surge current flows into the n type buried layer 5. Thereby, an input voltage is clamped to a value which is equal to a breakdown voltage of the p-n junction diode D1 between the n type region 6a and p type region 9. Namely, holes are implanted to a low potential p type layer 9 from the n type region 6a, causing a current I1 to flow and absorbing a surge pulse. A backward surge current operates the p-n junction diode between the n type region 6a and the p type diffused layer 9 and an input voltage is clamped to a voltage (GND-VF) which is equal to a difference between the ground voltage and forward voltage VF of diode, causing electrons to be implanted to the side of p type diffused layer 9 from the n type region 6a.
摘要翻译：目的：通过形成n +型埋层作为保护电阻并使用由n +型区域和p型扩散区域构成的结二极管来吸收正和负浪涌脉冲。构成：当正向浪涌脉冲进入输入端侧的电极时，在浪涌电流流入n +型埋层5的同时由于电阻而下降，由此，将输入电压钳位到等于n +型区域6a和p型区域9之间的pn结二极管D1的击穿电压。即，从n +型区域6a将空穴注入到低电位p型层9中，导致电流I1流动并吸收浪涌脉冲。反向浪涌电流在n +型区域6a和p型扩散层9之间操作pn结二极管，并且将输入电压钳位到等于接地电压和二极管的正向电压VF，使电子从n +型区域6a注入到p型扩散层9侧。

2. 发明专利

JPS6123355A Apparatus for preventing electrostatic breakdown of semiconductor 失效
标题翻译：防止半导体静电破坏的装置
公开(公告)号：JPS6123355A
公开(公告)日：1986-01-31
申请号：JP14238984
申请日：1984-07-11
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HAIJIMA MIKIO , TAKIGAWA AKIRA , IHARA HIROSHI , IWASAKI ISAO , WATABE TOMOYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0248
摘要： PURPOSE:To absorb both forward and backward surge pulses by forming an n type buried layer as a protection resistance and allowing an input pulse to escape through utilization of the forward and backward npn transistor comprising an n type semiconductor region, p type diffused region and n type diffused region. CONSTITUTION:When a forward surge pulse enters the electrode in the side of input terminal B, a voltage drops due to a resistance R while a surge current I0 flows in the n type buried layer 5. Thereby, a forward npn transistor Q1 (composed of the n type semiconductor region 6a, p type semiconductor region 9 and n type semiconductor 10) operates and a current I1 flows into the ground electrode passing through the electrode on n type diffused region 10. When a backward surge pulse enters, a negative surge current flows to the side of circuit A through the n type buried layer 5, resulting in voltage drop. Therefore, a backward npn transistor Q2 where the p type region 9 is formed as the base, the n type diffused region 10 as the collector and n type semicondutor region as the emitter operates and a current I2 flows to the side of input terminal B.
摘要翻译：目的：通过形成n +型埋层作为保护电阻并允许输入脉冲通过利用包括n +型半导体区域的正向和反向npn晶体管来逸出来吸收正向和反向浪涌脉冲， p型扩散区和n +型扩散区。构成：当正向浪涌脉冲进入输入端子B侧的电极时，由于电阻R的电压下降，而浪涌电流I0在n +型埋层5中流动。因此，正向npn晶体管Q1 （由n型半导体区域6a，p型半导体区域9和n +型半导体10构成）工作，电流I1流入通过n +型扩散区域10上的电极的接地电极当反向浪涌脉冲进入时，负的浪涌电流通过n +型埋层5流向电路A侧，导致电压下降。因此，作为基极形成p型区域9的后向npn晶体管Q2，作为集电极的n +型扩散区域10和作为发射极的n +型半导体区域工作，电流I2流向输入端B.

3. 发明专利

JPS6123354A Apparatus for preventing electrostatic breakdown of semiconductor device 失效
标题翻译：防止半导体器件静电破坏的装置
公开(公告)号：JPS6123354A
公开(公告)日：1986-01-31
申请号：JP14238884
申请日：1984-07-11
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： IHARA HIROSHI , HAIJIMA MIKIO , TAKIGAWA AKIRA , WATABE TOMOYUKI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0248
摘要： PURPOSE:To improve an electrostatic breakdown level up to about 100V by forming the n type diffused region by diffusion of emitter as a protection resistance and by absorbing the forward and backward surge pulse by allowing an input pulse to escape to Vcc through utilization of the npn transistor consisting of such n type region, p type diffused region and n type region. CONSTITUTION:In case the forward surge pulse enters the electrode in the side of input terminal, a voltage drops due to a resistance R while a surge current Io flows into the n diffused region 10. Thereby, the backward npn transistor, where the n type diffused region 10 used as the collector, the p type diffused region 9 as the base and the n type region 6a as the emitter, operatesk. Since the emitter side is connected to a high voltage side, electrons are implanted to the p type region 9 as the base from the n type region 6a which becomes the emitter, causing a current I1 to flow in order to absorb surge pulse. When the backward surge pulse enters the electrode in the input terminal side, a current I2 flows to the input terminal side from Vcc side, absorbing a surge pulse.
摘要翻译：目的：为了通过扩散发射极作为保护电阻形成n +型扩散区域，并通过允许输入脉冲通过利用来将输入脉冲逸出到Vcc来吸收正向和反向浪涌脉冲，来提高高达约100V的静电击穿电平由n +型晶体管组成的n +型区域，p型扩散区域和n +型区域。构成：在正向浪涌脉冲进入输入端侧的电极的情况下，由于电阻R的电压下降，而浪涌电流Io流入n +扩散区域10.因此，后向npn晶体管，其中用作集电极的n +型扩散区域10，作为基极的p型扩散区域9和作为发射极的n +型区域6a。由于发射极侧连接到高电压侧，因此电子从作为发射极的n +型区域6a注入作为基极的p型区域9，导致电流I1流过以吸收浪涌脉冲。当反向浪涌脉冲进入输入端侧的电极时，电流I2从Vcc侧流向输入端侧，吸收浪涌脉冲。

4. 发明专利

JPS6143466A Semiconductor electrostatic breakdown preventing device 失效
标题翻译：半导体静电防止破坏装置
公开(公告)号：JPS6143466A
公开(公告)日：1986-03-03
申请号：JP16499884
申请日：1984-08-08
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HAIJIMA MIKIO , TAKIGAWA AKIRA , IHARA HIROSHI , WASHIO KATSUYOSHI , IWASAKI ISAO , WATANABE TOMOYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0248
摘要： PURPOSE:To contrive to improve the preventing level of electrostatic breakdown by a method wherein the surge pulse inputted is absorbed by the forward or reverse operation of the transistor wherein the n type semiconductor region or the n type semiconductor region is used as its emitter or its base. CONSTITUTION:In case forward surge pulse + is inputted in the electrode on the side of the input terminal, the surge current I0 travels through a p type diffusion region 9. During that travel, the voltage drops as much as the resistance component R. By this voltage drop, the forward npn transistor TRQ1; wherein the diffusion layer 9 is used as its base, an n type semiconductor region 6a is used as its collector and an n type semiconductor region 10 is used as its emitter; is actuated in the vicinity of an electrode 9a. That is, when the voltage of the surge pulse inputted rises higher than a voltage that the breakdown voltage VBE of the npn transistor TRQ1 is added to the high potential VCC, the voltage is clamped and the surge pulse is absorbed, while in case inverse surge pulse - is inputted in the electrode on the side of the input terminal, the voltage drops during the time when the negative surge current gets to the side of a circuit A through the diffusion layer 9 and when the diode D1 is actuated between a p type substrate 4 and an n type buried layer 5 and the voltage of the surge pulse drops lower than a difference between the earth voltage and the forward voltage VF, the voltage is clamped and the surge pulse is absorbed.
摘要翻译：目的：通过其中输入的浪涌脉冲被其中n +型半导体区域或n +型半导体区域的正向或反向操作吸收的方法来改进防止静电击穿水平用作其发射体或其基底。构成：在输入端子侧的电极中输入正向浪涌脉冲+的情况下，浪涌电流I0通过ap型扩散区域9行进。在该行程中，电压下降与电阻成分R一样多。由此电压降，正向npn晶体管TRQ1; 其中使用扩散层9作为其基极，使用n +型半导体区域6a作为其集电极，并且使用n +型半导体区域10作为其发射极; 在电极9a附近被致动。也就是说，当输入的浪涌脉冲的电压上升到高于npn晶体管TRQ1的击穿电压VBE加到高电位VCC的电压时，电压被钳位并且浪涌脉冲被吸收，而在反向浪涌的情况下脉冲输入到输入端子侧的电极中，在负电涌电流通过扩散层9到达电路A的一侧的时间期间，当二极管D1在ap < >型衬底4和n +型埋层5，并且浪涌脉冲的电压降低到接地电压和正向电压VF之间的差，电压被钳位并且浪涌脉冲被吸收。

5. 发明专利

JPS6174366A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS6174366A
公开(公告)日：1986-04-16
申请号：JP19472784
申请日：1984-09-19
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HOYA KAZUO , WATABE TOMOYUKI , HAIJIMA MIKIO , TAKIGAWA AKIRA , HAYASHI MAKOTO
IPC分类号： H01L21/8226 , H01L21/331 , H01L27/082 , H01L29/73 , H01L29/732
CPC分类号： H01L29/7325
摘要： PURPOSE:To improve the withstand voltage of a p-n-p subtransistor without increasing the manhour by a method wherein an n-type impurity of the concentration higher than that of the n-type Si layer is diffused in the n-type Si layer including the junction parts, which are formed of the n-type Si layer and the p-type diffusion layers. CONSTITUTION:An n type Si layer 2 is isolated by groove parts 3, and a region I, a region II and a region III are respectively used as a p-n-p sub-transistor forming part, an n-p-n transistor forming part and an IIL forming part. Donors are ion-implanted in the surfaces of the regions I and III, and GN (high- concentration n-type) regions II are formed. As a result, elongation of a depletion layer, which spreads from the substrate p-type layer, is reduced. Accordingly, the withstand voltage of the p-n-p sub-transistor can be improved.
摘要翻译：目的：为了提高pnp副晶体管的耐受电压，而不增加工作空间，其中浓度比n型Si层高的n型杂质扩散到包含接合部分的n型Si层中由n型Si层和p型扩散层形成。构成：n型Si层2被沟槽部分3隔离，区域I，区域II和区域III分别用作pnp子晶体管形成部分，npn晶体管形成部分和IIL 形成部分。在区域I和III的表面离子注入供体，形成GN（高浓度n型）区域II。结果，从衬底p型层扩散的耗尽层的伸长率降低。因此，可以提高p-n-p子晶体管的耐受电压。

6. 发明专利

JPS6151871A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6151871A
公开(公告)日：1986-03-14
申请号：JP17327884
申请日：1984-08-22
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TAKIGAWA AKIRA , HAIJIMA MIKIO , TANIZAKI YASUNOBU
IPC分类号： H01L29/08 , H01L21/331 , H01L29/73 , H01L29/735
CPC分类号： H01L29/735
摘要： PURPOSE:To improve element characteristics, such as a current amplification factor, frequency characteristics, etc. by forming a stepped section between an emitter region and a collector region in a lateral type bipolar transistor. CONSTITUTION:A body in which an N epitaxial layer 2 is formed to a P type semiconductor substrate 1 is used as a base body, and etching grooves 21 are shaped to the predetermined sections of the N type epitaxial layer 2. P type diffusion layers 4 are formed to isolate electrically independent element forming regions a1, a2. Openings are bored partially to a surface oxide film 71 shaped onto the whole surface once through etching. An silicon oxide layer 72 formed by using plasma is deposited on the surface oxide films 71. Anisotropic dry etching is conducted. Consequently, only the silicon oxide layers 72 on flat sections in the layer 72 are removed selectively. The silicon oxide layers 72 deposited on the inclined sections 22 of the region a1 are left. According to the etching, an emitter and a collector in a PNP transistor can be formed through self-alignment.
摘要翻译：目的：通过在横向型双极晶体管中的发射极区域和集电极区域之间形成台阶部分来改善元件特性，例如电流放大因子，频率特性等。构成：使用将N +外延层2形成于P型半导体基板1的主体作为基体，蚀刻槽21成形为N型的规定部分外延层2.形成P型扩散层4以隔离电独立的元件形成区域a1，a2。开口部分地通过蚀刻而部分地形成在整个表面上形成的表面氧化物膜71。通过使用等离子体形成的氧化硅层72沉积在表面氧化膜71上。进行各向异性干蚀刻。因此，仅选择性地去除层72中的平坦部分上的氧化硅层72。留下沉积在区域a1的倾斜部分22上的氧化硅层72。根据蚀刻，可以通过自对准形成PNP晶体管中的发射极和集电极。

7. 发明专利

JPS59191365A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59191365A
公开(公告)日：1984-10-30
申请号：JP6533483
申请日：1983-04-15
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KOWASE YASUAKI , INABA TOORU , TAKAGI TATSUITSU , TAKIGAWA AKIRA , TOKUOKA SUSUMU
IPC分类号： H01L27/04 , H01L21/822 , H01L23/60 , H01L27/02 , H01L27/06 , H01L29/866
CPC分类号： H01L27/0248
摘要： PURPOSE:To prevent electrostatic breakdown by isoplanar structure by forming high-concentration n type layer for extracting potential from an n type buried layer to one part of an island region on the n type buried layer so that the buried layer is used as a resistance section and employing a p-n junction as a protective diode. CONSTITUTION:An n buried layer 12 is formed to a p type Si substrate 11. n layers 14, 15 are formed, and an isoplanar oxide film 13 is formed to one part of the Si layer. A p type isolation section 18 is diffused so that a p type impurity is connected to the p type substrate 11. The high-concentration n type layers 14, 15 are separated by the isoplanar oxide film so that the n type buried layer 12 is used as a resistance section and formed at two positions. An Al electrode 16 is brought into ohmic-contact on one n type layer 14, and connected to an external terminal (PAD) for a chip. An Al electrode 17 is brought into ohmic-contact on the other n type layer 15, and connected to a base or an emitter in a transistor to be protected.
摘要翻译：目的：为了通过形成用于从n +型掩埋层将电位提取到n +型掩埋层的岛状区域的一部分的高浓度n +型层来防止由等面结构的静电破坏，使得掩埋层用作电阻部分并且使用pn结作为保护二极管。构成：对p型Si衬底11形成n +掩埋层12，形成n + +层14,15，并且在Si层的一部分上形成等平面氧化膜13。 p型隔离部分18扩散，使得p型杂质连接到p型衬底11.高浓度n +型层14,15被等面积氧化膜分离，使得n +型掩埋层12用作电阻部分并形成在两个位置。 Al电极16在一个n +型层14上形成欧姆接触，并连接到用于芯片的外部端子（PAD）。 Al电极17在另一个n +型层15上进行欧姆接触，并连接到要保护的晶体管中的基极或发射极。

8. 发明专利

JPS60226158A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60226158A
公开(公告)日：1985-11-11
申请号：JP8186784
申请日：1984-04-25
申请人： AKITA DENSHI KK , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IHARA HIROSHI , TAKIGAWA AKIRA , HAIJIMA MIKIO , WASHIO KATSUYOSHI , WATABE TOMOYUKI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
摘要： PURPOSE:To obtain an electrostatic breakdown preventing element to fit to a high integration process of IC by a method wherein the element is constitued in such a structure that the transistor consisting of the n type semiconductor layer, which is used as the base, either of the p type resistance region or the p type substrate, which is used as the emitter, and the other one, which is used as the collector, is actuated and surge pulse is absorbed. CONSTITUTION:When a forward surge pulse (+) is impressed on an electrode 12a on the side of the input terminal, surge current runs momentarily in the interior of a p type layer 9, voltage drop is caused by resistance in the interior of the p type layer9 p-n forward voltage is added in between the p type layer 9 and an n type region 6a. A p-n-p transistor Q1 consisting of the layer 9, which is used as its emitter, the region 6a, which is used as its base, and a p type substrate 4, which is used as its collector, is actuated to make positive surge escape rapidly to the earth potential. Meanwhile, when inverse surge pulse (-) is impressed on the electrode 12a on the side of the input terminal, an inverse p-n-p subtransistor Q2 consisting of the p type substrate 4, which is used as its emitter, the n type region 6a, which is used as its base, and the p type diffusion layer 9, which is used as the collector, is actuated and negative pulse is absorbed.

9. 发明专利

JPS61150231A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61150231A
公开(公告)日：1986-07-08
申请号：JP27092684
申请日：1984-12-24
申请人： HITACHI MICROCUMPUTER ENG , AKITA DENSHI KK , HITACHI LTD
发明人： TAKIGAWA AKIRA , HAIJIMA MIKIO , IHARA HIROSHI
IPC分类号： H01L21/764 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/761 , H01L29/73 , H01L29/732
摘要： PURPOSE:To prevent a parasitic PNP transistor from being formed, to improve characteristics of a transistor, and to manufacture the IC operating stably, by forming an N -type diffusion layer extended from an N -type buried layer between an N -type semiconductor region and an isolation P-type layer. CONSTITUTION:An N -type buried layer 2 is extended to below an isolation groove 4, and an N -type diffusion layer 9 with a high concentration is formed between the periphery of an N -type mesa semiconductor region 3a and an N -type buried layer extension. A portion of the N -type diffusion layer 9 serves as a collector taking-out section 8 where a collector electrode C is provided in a groove. In an IC structure having an NPN transistor so constructed, its base would be coupled to the isolation P-type diffusion layer in the peripheral groove when being saturated to result in a parasitic PNP sub-transistor. However, by forming the N -type diffusion layer 9 with a high concentration on the periphery acting as the base of the PNP sub-transistor, amplification factor alphaof the PNP sub-transistor is reduced and thus its operation is prevented. In this way, transistor characteristics can be improved and the transistor can be operated at a low consuming power.

10. 发明专利

JPS6080268A MANUFACTURE OF SEMICONDUCTOR IC DEVICE 失效
公开(公告)号：JPS6080268A
公开(公告)日：1985-05-08
申请号：JP18691683
申请日：1983-10-07
申请人： HITACHI MICROCUMPUTER ENG , AKITA DENSHI KK , HITACHI LTD
发明人： TAKIGAWA AKIRA , INABA TOORU , KOWASE YASUAKI , TAKAGI SHINICHI , IHARA HIROSHI
IPC分类号： H01L21/331 , H01L21/761 , H01L21/8226 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To obtain the titled device with improved characteristics by a method wherein, in providing the same semiconductor substrate with a bi-polar transistor element and an I L element, the semiconductor layer is thinned by the boring of a groove at the middle of the layer, where an isolation region is formed and then shallowed more than the depth of the base region of the bi-polar element. CONSTITUTION:Two N type buried region 13 are diffusion-formed in the surface layer part of the P type Si substrate 10, and an N type layer 12 is epitaxially grown over the entire surface including the regions, the parts of which layer containing the regions are then used as a bi-polar transistor element Q1 region a1 and an I L element region a2, respectively. Next, a wide groove 16 is bored between these regions, and a narrow groove 14 outside the regions; an insulation film is adhered over the entire surface, and an aperture is provided in the groove 14, and an aperture of the same size of that of the groove 14 in the groove 16. Thereafter, P type impurity ions are implanted therein, and next elongating diffusion is carried out, resulting in the formation of the P type isolation region 20 at a low level reaching the substrate. Accordingly, this region is shallowed more than the depths of a P type base region 22 and a graft structural base region 32.

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