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1. 发明授权

US06460168B1 Method of designing power supply circuit and semiconductor chip 有权
标题翻译：设计电源电路和半导体芯片的方法
公开(公告)号：US06460168B1
公开(公告)日：2002-10-01
申请号：US09446722
申请日：2000-03-27
申请人： Akira Yamamoto , Shirou Sakiyama , Hiroyuki Nakahira , Masayoshi Kinoshita , Katsuji Satomi , Jun Kajiwara , Shinichi Yamamoto
发明人： Akira Yamamoto , Shirou Sakiyama , Hiroyuki Nakahira , Masayoshi Kinoshita , Katsuji Satomi , Jun Kajiwara , Shinichi Yamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/50 , G06F2217/78 , H01L27/088 , H01L27/11807 , H01L2224/05554 , H01L2224/49171 , H02M3/1588 , H02M7/003 , Y02B70/1466
摘要： A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.
摘要翻译：根据本发明的电源电路是形成在半导体芯片上的电源电路，包括：输出电源电压的输出晶体管部分; 以及用于控制输出晶体管部分的控制电路。输出晶体管部分布置在半导体芯片的外部输入/输出端子附近。

2. 发明授权

US06684378B2 Method for designing power supply circuit and semiconductor chip 有权
标题翻译：设计电源电路和半导体芯片的方法
公开(公告)号：US06684378B2
公开(公告)日：2004-01-27
申请号：US10012731
申请日：2001-11-05
申请人： Akira Yamamoto , Shirou Sakiyama , Hiroyuki Nakahira , Masayoshi Kinoshita , Katsuji Satomi , Jun Kajiwara , Shinichi Yamamoto
发明人： Akira Yamamoto , Shirou Sakiyama , Hiroyuki Nakahira , Masayoshi Kinoshita , Katsuji Satomi , Jun Kajiwara , Shinichi Yamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/50 , G06F2217/78 , H01L27/088 , H01L27/11807 , H01L2224/05554 , H01L2224/49171 , H02M3/1588 , H02M7/003 , Y02B70/1466
摘要： A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.
摘要翻译：根据本发明的电源电路是形成在半导体芯片上的电源电路，包括：输出电源电压的输出晶体管部分; 以及用于控制输出晶体管部分的控制电路。输出晶体管部分布置在半导体芯片的外部输入/输出端子附近。

3. 发明授权

US6150800A Power circuit including inrush current limiter, and integrated circuit including the power circuit 有权
标题翻译：包括浪涌电流限制器的电源电路和包括电源电路的集成电路
公开(公告)号：US6150800A
公开(公告)日：2000-11-21
申请号：US395971
申请日：1999-09-15
申请人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
发明人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
IPC分类号： G05F1/56 , G05F1/573 , G05F1/575 , H02H9/02 , G05F1/40
CPC分类号： G05F1/573 , G05F1/575 , Y10S323/908
摘要： A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.
摘要翻译：描述了一种电源电路，其包括用于在电源电路的初始操作期间防止产生浪涌电流的装置，而不增加电源电路的尺寸。电源电路包括用于从电源向输出端子提供电流的输出晶体管，以及差分放大器，用于根据预设的方式控制由输出晶体管提供的电流，以调节输出端子处的电压参考电压。在差分放大器的输出级的电流路径上提供限制晶体管作为源极跟随器。使用限制晶体管的源极电位来控制输出晶体管的栅极电位。在电源电路开始工作之前，操作控制器对电容器充电以控制限流晶体管的栅极电位，使得在电源电路的初始操作期间，通过使用电流源来放电电容器。因此，在电源电路的初始动作期间，限制晶体管的栅极电位逐渐降低，同时输出晶体管的栅极 - 源极电压逐渐增大。结果，可以抑制浪涌电流的产生。

4. 发明授权

US06429633B1 Switching regulator and LSI system 失效
标题翻译：开关稳压器和LSI系统
公开(公告)号：US06429633B1
公开(公告)日：2002-08-06
申请号：US09530267
申请日：2000-04-28
申请人： Jun Kajiwara , Katsuji Satomi , Shiro Sakiyama , Masayoshi Kinoshita , Katsuhiro Ootani
发明人： Jun Kajiwara , Katsuji Satomi , Shiro Sakiyama , Masayoshi Kinoshita , Katsuhiro Ootani
IPC分类号： G05F140
CPC分类号： H03K17/164
摘要： In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.
摘要翻译：在开关稳压器中，开关噪声降低，保持高的转换效率。开关调节器包括具有不同导通电阻的多个输出开关晶体管21至23，它们在接通操作中工作时导通电阻的下降顺序，并且在关断操作中以导通电阻的升序操作。以这种方式，可以在开关操作中抑制突然的电流变化，从而减少从寄生电感器102得到的di / dt噪声。

5. 发明授权

US06307360B1 Switching regulator DC/DC converter, and LSI system provided with switching regulator 有权
标题翻译：开关稳压器DC / DC转换器和配有开关稳压器的LSI系统
公开(公告)号：US06307360B1
公开(公告)日：2001-10-23
申请号：US09673851
申请日：2000-10-23
申请人： Jun Kajiwara , Shiro Sakiyama , Masayoshi Kinoshita , Katsuji Satomi , Katsuhiro Ootani
发明人： Jun Kajiwara , Shiro Sakiyama , Masayoshi Kinoshita , Katsuji Satomi , Katsuhiro Ootani
IPC分类号： G05F1563
CPC分类号： H02M1/36 , H02M1/32 , H02M3/1588 , H02M2001/0009 , Y02B70/1466
摘要： The switching regulator of a synchronous rectifying mode comprises the first and second switches SW1, SW2 arranged in series between the power source Vdd and the ground Vss, the switch control unit 1 which controls the on-off operation of the switches SW1, SW2, and the smoothing circuit 4 which smoothes the output node potential Vnd. When the signal Sc1 indicates that the output node potential Vnd goes below the first reference potential Vr1 which is the reference to detect the occurrence of the inrush current while the first switch SW1 is in the ON state, the control circuit 10 turns off the first switch SW1. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW1, so that it is unnecessary to provide a resistance element for detecting the inrush current.
摘要翻译：同步整流模式的开关调节器包括串联布置在电源Vdd和接地Vss之间的第一和第二开关SW1，SW2，开关控制单元1，其控制开关SW1，SW2的开关操作，以及平滑电路4，其平滑输出节点电位Vnd。当信号Sc1表示输出节点电位Vnd低于第一基准电位Vr1时，第一参考电位Vr1是第一开关SW1处于导通状态时检测涌流的发生的基准，控制电路10关闭第一开关 SW1。因此，通过利用由于第一开关SW1的导通电阻引起的电压降来进行浪涌电流的检测，从而不需要提供用于检测浪涌电流的电阻元件。

6. 发明授权

US07235855B2 Semiconductor device having a layout configuration for minimizing crosstalk 有权
标题翻译：具有用于最小化串扰的布局配置的半导体器件
公开(公告)号：US07235855B2
公开(公告)日：2007-06-26
申请号：US11190854
申请日：2005-07-28
申请人： Katsuji Satomi
发明人： Katsuji Satomi
IPC分类号： H01L29/00
CPC分类号： G11C7/18 , G11C5/063 , G11C8/14
摘要： Over a memory cell array region of a static RAM (random access memory), dummy wire patterns are formed such that each dummy wire pattern covers 2×2 horizontally and vertically-adjacent intersection points of word lines and bit lines, and horizontally-running wire channels and vertically-running wire channels are formed between the dummy wire patterns in a lattice configuration. Then, a signal line is automatically arranged to extend through any of the wire channels. The dummy wire patterns are provided in a layer lying on the word lines, and the signal line is provided as a metal line extending in the same layer as that of the dummy wire patterns.
摘要翻译：在静态RAM（随机存取存储器）的存储单元阵列区域中，形成虚拟线图案，使得每个虚拟线图案覆盖字线和位线的2×2水平和垂直相邻交点，以及水平运行的线通道和在虚拟线图案之间以格子构型形成垂直运行的线通道。然后，信号线被自动布置成延伸通过任何线路通道。虚设线图案设置在位于字线上的层中，并且信号线被设置为与虚拟线图案相同的层延伸的金属线。

7. 发明授权

US07136318B2 Semiconductor memory device and circuit layout of dummy cell 有权
标题翻译：半导体存储器件和虚拟电池的电路布局
公开(公告)号：US07136318B2
公开(公告)日：2006-11-14
申请号：US11156706
申请日：2005-06-21
申请人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
发明人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/12 , G11C7/227 , G11C11/413
摘要： A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.
摘要翻译：虚拟单元包括两个串联的截止状态晶体管，由这两个晶体管形成的串联电路的一端与恒定电压源连接，串联电路的另一端与复制位线连接。这抑制了从复制位线流向虚拟单元的泄漏电流，从而给读出放大器电路提供了最佳的启动时序。

8. 发明申请

US20050286323A1 Semiconductor memory device and circuit layout of dummy cell 有权
标题翻译：半导体存储器件和虚拟电池的电路布局
公开(公告)号：US20050286323A1
公开(公告)日：2005-12-29
申请号：US11156706
申请日：2005-06-21
申请人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
发明人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
IPC分类号： G11C7/08 , G11C7/12 , G11C11/413 , G11C29/00
CPC分类号： G11C7/08 , G11C7/12 , G11C7/227 , G11C11/413
摘要： A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.
摘要翻译：虚拟单元包括两个串联的截止状态晶体管，由这两个晶体管形成的串联电路的一端与恒定电压源连接，串联电路的另一端与复制位线连接。这抑制了从复制位线流向虚拟单元的泄漏电流，从而给读出放大器电路提供了最佳的启动时序。

9. 发明申请

US20080043554A1 Semiconductor memory device realizing high-speed access 有权
公开(公告)号：US20080043554A1
公开(公告)日：2008-02-21
申请号：US11703785
申请日：2007-02-08
申请人： Marefusa Kurumada , Katsuji Satomi
发明人： Marefusa Kurumada , Katsuji Satomi
IPC分类号： G11C7/12 , G06F12/00
CPC分类号： G11C7/18 , G11C7/12 , G11C8/12 , G11C2207/002
摘要： In data read, a single read global bit line is shared with a plurality of local bit lines.

10. 发明申请

US20060050586A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060050586A1
公开(公告)日：2006-03-09
申请号：US11218601
申请日：2005-09-06
申请人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
发明人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C7/08 , G11C7/14 , G11C7/227 , G11C11/419 , H01L27/1104
摘要： A memory array, a sense amplifier circuit, a replica circuit and a dummy cell are disposed. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.
摘要翻译：存储器阵列，读出放大器电路，复制电路和虚设单元。复制电路具有与存储单元相同的元件，并且包括输出其电平对应于提供给公共复制位线的级数的信号的多个复制单元。虚拟单元作为负载与公共副本位线连接。虚拟单元的驱动晶体管的源极与处于高电平的电源连接。这抑制了从复制位线流向虚拟电池的泄漏电流。

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