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1. 发明授权

US4618873A Thin film device 失效
标题翻译：薄膜装置
公开(公告)号：US4618873A
公开(公告)日：1986-10-21
申请号：US621683
申请日：1984-06-18
申请人： Akira Sasano , Kouichi Seki , Hideaki Yamamoto , Toru Baji , Toshihisa Tsukada
发明人： Akira Sasano , Kouichi Seki , Hideaki Yamamoto , Toru Baji , Toshihisa Tsukada
IPC分类号： H01L21/02 , H01L21/822 , H01L21/84 , H01L27/04 , H01L27/146 , H01L29/45 , H01L31/02 , H01L29/78
CPC分类号： H01L28/20 , H01L21/84 , H01L27/14643 , H01L29/458
摘要： In a thin film device having a hydrogenated amorphous silicon film, a metal layer is formed on the hydrogenated amorphous silicon film and then the metal layer is removed. A resulting reaction layer formed on the hydrogenated amorphous silicon film is used as a resistor.
摘要翻译：在具有氢化非晶硅膜的薄膜器件中，在氢化非晶硅膜上形成金属层，然后除去金属层。形成在氢化非晶硅膜上的反应层用作电阻。

2. 发明授权

US06286354B1 Rolling mill and rolling method and rolling equipment 失效
标题翻译：轧机和轧制方法及轧制设备
公开(公告)号：US06286354B1
公开(公告)日：2001-09-11
申请号：US09155766
申请日：1999-08-23
申请人： Toshiyuki Kajiwara , Yoshihiko Iida , Yasutsugu Yoshimura , Kouichi Seki , Ryohei Konose , Mitsuo Nihei
发明人： Toshiyuki Kajiwara , Yoshihiko Iida , Yasutsugu Yoshimura , Kouichi Seki , Ryohei Konose , Mitsuo Nihei
IPC分类号： B21B3100
CPC分类号： B21B37/28 , B21B13/023 , B21B27/10 , B21B2013/026 , B21B2013/028 , B21B2269/04 , B21B2269/06
摘要： The work rolls of two sets of roller groups are held within one-piece metal chock in a rolling mill. A one-piece metal chock in which the driving side and operating side are separate then provides support at the upper part of the rolling material, with support similarly being provided at the lower part using another pair of single piece metal chocks. Two sets of roll groups can then be arranged close to each other, strip walking and strip curving can be prevented, and a rolling mill, rolling method and rolling installation that are easy to maintain and provide superior rolling efficiency can be provided.
摘要翻译：两组辊组的工作辊在轧机中保持在一体式金属轴承座内。其中驱动侧和操作侧分离的一体式金属轴承座在该轧制材料的上部提供支撑，同时使用另一对单件金属轴承座在下部设置支撑件。可以将两组辊组彼此靠近地布置，可以防止剥离走行和带状弯曲，并且可以提供易于维护并提供优异的轧制效率的轧机，轧制方法和轧制设备。

3. 发明授权

US06288941B1 Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks 失效
标题翻译：具有划分为存储块的存储单元阵列的电可擦除半导体非易失性存储器件
公开(公告)号：US06288941B1
公开(公告)日：2001-09-11
申请号：US08379020
申请日：1995-01-27
申请人： Kouichi Seki , Toshihiro Tanaka , Hitoshi Kume , Takeshi Wada , Tadashi Muto
发明人： Kouichi Seki , Toshihiro Tanaka , Hitoshi Kume , Takeshi Wada , Tadashi Muto
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C8/12 , G11C16/16
摘要： An electrically erasable semiconductor nonvolatile memory device has an array of memory cells arranged in rows and columns and one or more information erasure signal generating circuits. Each of the memory cells of the memory cell array includes a field-effect transistor element having a control gate connected with a word line conductor extending in a direction of the rows, a floating gate where carriers may be accumulated, a drain connected with a data line conductor extending in the direction of the columns and a source connected with a source conductor. The memory cell array may be divided into a plurality of memory blocks so as to have boundaries in the row direction or in the column direction, with the source conductors arranged in the row direction or in the column direction. Information erasure signals may be supplied to the source conductors or data line conductors with a time delay therebetween.
摘要翻译：电可擦除半导体非易失性存储器件具有排列成行和列的存储单元阵列和一个或多个信息擦除信号发生电路。存储单元阵列的每个存储单元包括场效应晶体管元件，其具有与沿着行的方向延伸的字线导体连接的控制栅极，可以累积载流子的浮置栅极，与数据相连的漏极线导体沿列的方向延伸，源极与源极连接。存储单元阵列可以被划分为多个存储块，以便在行方向或列方向上具有沿着行方向或列方向布置的源极的边界。信息擦除信号可以以它们之间的时间延迟提供给源极导体或数据线导体。

4. 发明授权

US5914697A Method of fabricating radio device helical antennas 失效
标题翻译：制造无线电设备螺旋天线的方法
公开(公告)号：US5914697A
公开(公告)日：1999-06-22
申请号：US952695
申请日：1997-12-02
申请人： Kouichi Seki
发明人： Kouichi Seki
IPC分类号： H01F21/06 , H01Q1/24 , H01Q1/36 , H01Q1/38 , H01Q5/10 , H01Q9/30 , H01Q11/08
CPC分类号： H01Q11/08 , H01Q1/242 , H01Q1/362
摘要： A portable radio device helical antenna 1 is fabricated by a method wherein the cutting boss component 6 of a molded element 7, that has a spirally cut groove 4 formed around an insulator and that has a mounting component 3 at one end and the boss component 6 at the other end, is chucked, the components are metal plated, the metal layer is then removed except from the groove 4 and mounting component 3, the boss component 6 is then cut off and that location is machined, and a radio device base plate fixing hole 9 is formed in the mounting component 3. The mounting component 3 is then mounted on the base plate of a radio device main body.
摘要翻译： PCT No.PCT / JP97 / 00760 Sec。 371日期1997年12月2日第 102（e）日期1997年12月2日PCT 1997年3月11日PCT公布。 WO97 / 37400 PCT出版物日期1997年10月9日便携式无线电设备螺旋天线1通过一种方法制造，其中模制元件7的切割凸台部件6具有围绕绝缘体形成并且在一端具有安装部件3的螺旋切割凹槽4 并且另一端的凸台部件6被卡住，部件被金属镀覆，然后除了凹槽4和安装部件3之外除去金属层，然后将凸台部件6切断并且该位置被加工，以及在安装部件3中形成无线电设备基板固定孔9.安装部件3然后安装在无线电设备主体的基板上。

5. 发明授权

US5371023A Gate circuit, semiconductor integrated circuit device and method of fabrication thereof, semiconductor memory and microprocessor 失效
标题翻译：门电路，半导体集成电路器件及其制造方法，半导体存储器和微处理器
公开(公告)号：US5371023A
公开(公告)日：1994-12-06
申请号：US895815
申请日：1992-06-09
申请人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
发明人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
IPC分类号： H01L27/06 , H01L27/105 , H01L21/20
CPC分类号： H01L27/105 , H01L27/0623
摘要： A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.
摘要翻译：公开了一种新颖的门电路。第一半导体开关包括连接在第一电位电平和输出节点之间的一对主端子，其中响应于具有第一逻辑电平和第二逻辑电平的输入信号而保持高阻抗状态，并且阻抗状态仅在输入信号从第一逻辑电平变化到第二逻辑电平的过渡期间从高变化为低电平。第二半导体开关包括插入在与第一电位电平不同的第二电位电平和输出节点之间的一对主端子，其中响应于输入信号保持高阻抗状态，并且阻抗状态从高变为仅在输入信号从第二逻辑电平变为第一逻辑电平的瞬态期间为低电平。

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