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    • 3. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08711632B2
    • 2014-04-29
    • US13425860
    • 2012-03-21
    • Akira Katayama
    • Akira Katayama
    • G11C11/34
    • G11C11/1673
    • The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. The first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell. The second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to the reading current of the second reference cell.
    • 控制电路在第一存储单元的电阻值全部增加的状态下选择具有通过接通第一选择晶体管而提供的最大读取电流的第一存储单元作为第一参考单元。 控制电路在第二存储单元的电阻值全部增加的状态下选择具有通过接通第二选择晶体管而提供的最大读取电流的第二存储单元作为第二参考单元。 第一参考电流设置电路将通过将第一调整电流加到第一参考单元的读取电流而获得的电流作为第一参考电流。 第二基准电流设定电路将通过将第二调整电流加到第二参考单元的读取电流而获得的电流作为第二参考电流。
    • 5. 发明申请
    • INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
    • 信息处理设备和信息处理方法
    • US20120054480A1
    • 2012-03-01
    • US13211392
    • 2011-08-17
    • Akira KatayamaYoshinori OgakiMakoto KorehisaKayo Watanabe
    • Akira KatayamaYoshinori OgakiMakoto KorehisaKayo Watanabe
    • G06F1/26G06F9/00
    • H04N5/775G06F1/266G06F1/3206G06F1/3287Y02D10/171
    • An information processing apparatus includes a main switch configured to receive on/off-instructions for power supply from a user, a predicting section configured to predict a time period during which a possibility that the main switch receives an on-instruction is high, a connector section capable of connecting an electronic apparatus including a display screen, a communication establishing section configured to execute processing to establish a state allowing communication with an electronic apparatus connected to the connector section, a black-screen output section capable of outputting a black-screen signal to the electronic apparatus via the connector section, and a startup section configured to start, during a time period predicted by the predicting section and when the main switch is off, the communication establishing section and the black-screen output section, and to cause the black-screen output section to continue to output the black-screen signal until the main switch is turned on.
    • 一种信息处理装置,包括被配置为接收来自用户的供电的接通/关闭指令的主开关,被配置为预测主开关接收指令的可能性高的时间段的预测部,连接器 能够连接包括显示屏幕的电子设备的通信部分,通信建立部分,被配置为执行处理以建立允许与连接到连接器部分的电子设备进行通信的状态;黑屏输出部分,能够输出黑屏信号 以及启动部,被配置为在所述预测部所预测的时间段和所述主开关断开时开始所述通信建立部和所述黑屏输出部,并且使所述启动部 黑屏输出部分继续输出黑屏信号,直到主开关为t 结束了
    • 6. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08077493B2
    • 2011-12-13
    • US12635552
    • 2009-12-10
    • Akira Katayama
    • Akira Katayama
    • G11C5/06G11C8/08G11C7/00
    • G11C8/08G11C7/22G11C7/227G11C11/413
    • A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory cell including one pair of cross-connected inverters including a transistor, a first dummy transistor having a threshold voltage which has a certain relationship with a threshold voltage of the transistor of the memory cell, a dummy bit line connected to one end of the first dummy transistor, and the dummy bit line charged so as to have a predetermined voltage, a dummy transistor control circuit configured to control conduction of the first dummy transistor, and a word line driver configured to supply a word line voltage to the word line connected to the selected memory cell, and the word line driver configured to change a rise time of the word line voltage in accordance with a change in a voltage of the dummy bit line.
    • 半导体存储器件包括:存储单元阵列,其在字线和位线的每个交叉处设置多个存储单元,所述存储单元包括一对交叉连接的反相器,包括晶体管,具有阈值电压的第一虚拟晶体管,其具有 与存储单元的晶体管的阈值电压有一定关系,连接到第一虚拟晶体管的一端的虚拟位线和被充电以具有预定电压的虚拟位线;虚拟晶体管控制电路,被配置为 控制第一虚拟晶体管的导通,以及被配置为向连接到所选择的存储单元的字线提供字线电压的字线驱动器,以及字线驱动器,被配置为根据字线电压改变字线电压的上升时间 虚拟位线的电压发生变化。
    • 7. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20080137465A1
    • 2008-06-12
    • US11947241
    • 2007-11-29
    • Akira Katayama
    • Akira Katayama
    • G11C5/14
    • G11C11/417G11C5/147
    • A semiconductor memory device includes a memory cell which includes first and second inverter circuits. Each of the first and second inverter circuits includes a load transistor which includes a source connected to a first power supply terminal, and a driving transistor which includes a drain connected to a drain of the load transistor via a memory node, a gate connected to a gate of the load transistor, a source connected to a second power supply terminal, and a back gate connected to a third power supply terminal. A first power supply voltage is applied to the first power supply terminal. A ground voltage is applied to the second power supply terminal. A source voltage higher than the ground voltage is applied to the third power supply terminal.
    • 半导体存储器件包括具有第一和第二反相器电路的存储单元。 第一和第二反相器电路中的每一个包括负载晶体管,其包括连接到第一电源端子的源极和驱动晶体管,驱动晶体管包括经由存储器节点连接到负载晶体管的漏极的漏极,连接到 负载晶体管的栅极,连接到第二电源端子的源极和连接到第三电源端子的后栅极。 第一电源电压施加到第一电源端子。 接地电压施加到第二电源端子。 将高于地电压的源极电压施加到第三电源端子。
    • 10. 发明授权
    • Camera having the capability to detect and display insufficient shutter speed
    • 相机具有检测和显示不足的快门速度的能力
    • US06389235B1
    • 2002-05-14
    • US08711312
    • 1996-09-03
    • Masanori HasudaTetsuro GotoAkira Katayama
    • Masanori HasudaTetsuro GotoAkira Katayama
    • G03B708
    • G03B7/00G03B7/08
    • A camera includes a shutter unit for limiting the exposure time to a record medium, a shutter time setting unit for setting the shutter time of the shutter unit, a shutter drive and control unit for driving and controlling the shutter unit, a shutter condition detecting unit for detecting the condition of the shutter unit, a manifesting unit for manifesting the result detected by the shutter condition detecting unit, a manifestation control unit for driving and controlling the manifesting unit and a memory unit for previously storing inherent data to detect with the shutter condition detecting unit whereby a photographer is informed of the fact that the detection accuracy of the detecting element is insufficient for a shutter time, thus dealing with the situation. The manifestation control unit drives the shutter condition detecting unit, based on a shutter time set by the shutter time setting unit and inherent data stored in the memory unit, thus notifying the shutter condition detecting unit of the result.
    • 相机包括用于限制到记录介质的曝光时间的快门单元,用于设置快门单元的快门时间的快门时间设置单元,用于驱动和控制快门单元的快门驱动和控制单元,快门条件检测单元 用于检测快门单元的状态的显示单元,用于显示由快门条件检测单元检测到的结果的显示单元,用于驱动和控制显示单元的显示控制单元和用于预先存储用快门条件检测的固有数据的存储单元 检测单元,由此摄影者被告知检测元件的检测精度对于快门时间不足,因此处理该情况。 显示控制单元基于由快门时间设置单元设置的快门时间和存储在存储单元中的固有数据来驱动快门条件检测单元,从而通知快门条件检测单元的结果。