会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Method of manufacturing vertical power device
    • 垂直功率器件的制造方法
    • US5985708A
    • 1999-11-16
    • US816596
    • 1997-03-13
    • Akio NakagawaNaoharu SugiyamaTomoko MatsudaiNorio YasuharaAtsusi KurobeHideyuki FunakiYusuke KawaguchiYoshihiro Yamaguchi
    • Akio NakagawaNaoharu SugiyamaTomoko MatsudaiNorio YasuharaAtsusi KurobeHideyuki FunakiYusuke KawaguchiYoshihiro Yamaguchi
    • H01L27/12H01L29/73H01L29/739H01L29/786H01L21/8249
    • H01L29/78696H01L27/1203H01L29/7317H01L29/7394H01L29/78612H01L29/78624H01L29/78639H01L29/78645H01L29/78687
    • A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.
    • 一种半导体装置,包括具有第一导电型半导体衬底的垂直型半导体器件,形成在半导体衬底的表面上的漏极层,形成在漏极层的表面上的漏电极,第二导电型基极层, 所述半导体衬底的与所述漏极层相对的表面,选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层,形成在所述第一导电型源极层和所述第二导电型基极层上的源电极, 以及通过栅极绝缘膜与第一导电型源极层,第二导电型基极层和半导体基板接触形成的栅电极,以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置 不同于第二导电型基底层,和多晶 半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域,其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。
    • 6. 发明授权
    • High breakdown voltage semiconductor device
    • 高击穿电压半导体器件
    • US6163051A
    • 2000-12-19
    • US154041
    • 1998-09-16
    • Akio NakagawaTomoko MatsudaiHideyuki FunakiNorio Yasuhara
    • Akio NakagawaTomoko MatsudaiHideyuki FunakiNorio Yasuhara
    • H01L21/331H01L29/06H01L29/739H01L29/76H01L29/94H01L31/062H01L31/113H01L31/119
    • H01L29/66325H01L29/0696H01L29/7394H01L29/7398
    • A high breakdown voltage semiconductor device comprising a first base region of a first conductivity type, a second base region of a second conductivity type, which is formed in a surface region of the first base region, a first gate insulation film formed on an inner wall of a first LOCOS groove formed passing through the second base region to reach the first base region, a first gate electrode formed on the first gate insulation film, a first source region of a first conductivity type, which is formed in a surface region of the second base region around the first LOCOS groove in such a manner as to contact with the first gate insulating film, a first drain region formed in a surface region of the first base region in such a manner as to be spaced apart from the second base region, a source electrode formed on the first source region and on the second base region, and a drain electrode formed on the first drain region.
    • 一种高耐压电压半导体器件,包括第一导电类型的第一基极区域和形成在第一基极区域的表面区域中的第二导电类型的第二基极区域,形成在内壁上的第一栅极绝缘膜 形成为穿过第二基极区域以到达第一基极区域的第一LOCOS沟槽,形成在第一栅极绝缘膜上的第一栅极电极,形成在第一栅极绝缘膜的表面区域中的第一导电类型的第一源极区域, 第二基区,以与第一栅极绝缘膜接触的方式围绕第一LOCOS沟槽;第一漏极区,形成在第一基极区域的表面区域中,以与第二基极区域隔开; 形成在第一源极区域和第二基极区域上的源电极以及形成在第一漏极区域上的漏电极。