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1. 发明授权

US07195980B2 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 有权
标题翻译：具有高击穿电压的半导体器件及其制造方法
公开(公告)号：US07195980B2
公开(公告)日：2007-03-27
申请号：US11030432
申请日：2005-01-06
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

2. 发明授权

US06740952B2 High withstand voltage semiconductor device 有权
标题翻译：高耐压半导体器件
公开(公告)号：US06740952B2
公开(公告)日：2004-05-25
申请号：US10096357
申请日：2002-03-12
申请人： Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L2358
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/404 , H01L29/41725 , H01L29/42368 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a stable high withstand voltage lateral MISFET device which suppresses a gradual withstand voltage drop under high voltage and humidity conditions. In a MISFET device with a 700V breakdown drain voltage, the length of extension Mc (&mgr;m) of a field plate FP1 from the source side end of a thermal oxidization film, and the total insulating film thickness Tox (&mgr;m) directly below the extending tip of the field plate FP1, are greater than or equal to lower limit values Mcmin, Tcmin. As a result, even if there is growth in charge accumulation at the interface of the mold resin, the field strength at a point B and point C is always lower than at a point A, which suppresses a gradual withstand voltage drop and a gradual ON current drop, whereby it becomes possible to realize a withstand voltage of 700V.
摘要翻译：半导体器件包括稳定的高耐压横向MISFET器件，其抑制在高电压和湿度条件下的逐渐耐受电压降。在具有700V击穿漏极电压的MISFET器件中，场板FP1的距离热氧化膜的源侧端的延伸长度Mc（母体）的长度以及在延伸尖端正下方的总绝缘膜厚度Tox（母体）的场板FP1大于或等于下限值Mcmin，Tcmin。结果，即使模具树脂的界面处的电荷累积增加，点B和点C的场强始终低于点A处的场强，这抑制了逐渐的耐压降和逐渐的导通电流下降，从而可以实现700V的耐受电压。

3. 发明授权

US06525390B2 MIS semiconductor device with low on resistance and high breakdown voltage 有权
标题翻译：具有低导通电阻和高击穿电压的MIS半导体器件
公开(公告)号：US06525390B2
公开(公告)日：2003-02-25
申请号：US09793833
申请日：2001-02-27
申请人： Gen Tada , Akio Kitamura , Masaru Saito , Naoto Fujishima
发明人： Gen Tada , Akio Kitamura , Masaru Saito , Naoto Fujishima
IPC分类号： H01L2972
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/405 , H01L29/7818 , H01L29/7835
摘要： The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering. The semiconductor device according to the invention includes a p-type highly resistive semiconductor substrate; an n-type offset region in the surface portion of the substrate; a p-type base region in the surface portion of the substrate, the base region including an n+-type source region in the surface portion thereof, the base region including a channel portion in the extended portion thereof extended between the source region and the n-type offset region; a p-type offset region in the surface portion of the n-type offset region, the potential of the p-type offset region being fixed at the source potential; an n+-type drain region in the surface portion of the n-type offset region; a field oxide film on the p-type offset region; a gate oxide film on the channel portion of the base region; a gate electrode on the gate oxide film; a source electrode on source region; a drain electrode on the drain region; an interlayer film; a protection film; and a spiral polysilicon thin film on the field oxide film, one end of the thin film being connected to the drain electrode, another end of the thin film being connected to the source electrode, the thin film being formed of pn-diodes connected in series.
摘要翻译：本发明提供一种以低制造成本制造的半导体器件，其防止击穿电压降低。根据本发明的半导体器件包括p型高电阻半导体衬底; 在衬底的表面部分中的n型偏移区域; 在基板的表面部分中的p型基极区域，所述基极区域在其表面部分包括n +型源极区域，所述基极区域包括在其延伸部分中的沟道部分在源区域和n 型偏移区域; 在n型偏移区域的表面部分中的p型偏移区域，p型偏移区域的电位固定在源极电位; n型偏移区域的表面部分中的n +型漏极区域; p型偏移区上的场氧化膜; 在所述基极区域的沟道部分上的栅氧化膜; 栅氧化膜上的栅电极; 源区上的源电极; 漏极区域上的漏电极; 中间膜; 保护膜; 以及场氧化膜上的螺旋状多晶硅薄膜，薄膜的一端与漏电极连接，薄膜的另一端与源电极连接，薄膜由串联连接的pn二极管形成。

4. 发明申请

US20050127439A1 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 有权
公开(公告)号：US20050127439A1
公开(公告)日：2005-06-16
申请号：US11030432
申请日：2005-01-06
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/266 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.

5. 发明授权

US07687385B2 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 失效
标题翻译：具有高击穿电压的半导体器件及其制造方法
公开(公告)号：US07687385B2
公开(公告)日：2010-03-30
申请号：US11681525
申请日：2007-03-02
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

6. 发明授权

US5432370A High withstand voltage M I S field effect transistor and semiconductor integrated circuit 失效
标题翻译：高耐压M I S场效应晶体管和半导体集成电路
公开(公告)号：US5432370A
公开(公告)日：1995-07-11
申请号：US319774
申请日：1994-10-07
申请人： Akio Kitamura , Naoto Fujishima , Gen Tada
发明人： Akio Kitamura , Naoto Fujishima , Gen Tada
IPC分类号： H01L21/8238 , H01L27/04 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78
CPC分类号： H01L29/7816 , H01L27/088 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/408 , H01L29/7801 , H01L29/7809 , H01L29/0615
摘要： A semiconductor integrated circuit device is provided in which a highly reliable and low cost intelligent power semiconductor is mounted on the same substrate as that of a control circuit having a logic element, such as a low withstand voltage CMOS etc., and high withstand voltage and high current output MIS field effect transistor. A high withstand voltage MOSFET is composed of a vertical MOS portion 25 formed in one side of a laterally widened well layer 2 and a drain portion formed in the other side thereof and a second base layer 4 is formed on the surface of the well layer 2. Accordingly, a depletion layer widened just under the MOS portion 25 and the second base layer 4 develops a JFET effect at OFF time thereby realizing a high withstand voltage and reliability is provided since the generation of hot carriers can be prevented by the second base layer 4.
摘要翻译：提供了一种半导体集成电路器件，其中将高可靠性低成本的智能功率半导体安装在与具有低耐压CMOS等逻辑元件的控制电路相同的基板上，并具有高耐压，高电流输出MIS场效应晶体管。高耐压MOSFET由横向加宽的阱层2的一侧形成的垂直MOS部分25和形成在另一侧的漏极部分组成，第二基极层4形成在阱层2的表面上因此，在MOS部25正下方扩大的耗尽层，在第二基极层4的OFF时产生JFET效应，从而实现高的耐受电压，由于可以通过第二基极层防止热载流子的产生而提供可靠性 4。

7. 发明申请

US20070155144A1 SEMICONDUCTOR DEVICE EXHIBITING A HIGH BREAKDOWN VOLTAGE AND THE METHOD OF MANUFACTURING THE SAME 失效
标题翻译：展示高突变电压的半导体器件及其制造方法
公开(公告)号：US20070155144A1
公开(公告)日：2007-07-05
申请号：US11681525
申请日：2007-03-02
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/425
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

8. 发明授权

US06853034B2 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 失效
标题翻译：具有高击穿电压的半导体器件及其制造方法
公开(公告)号：US06853034B2
公开(公告)日：2005-02-08
申请号：US09756686
申请日：2001-01-09
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/266 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/76 , H01L23/58
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

9. 发明授权

US5436486A High voltage MIS transistor and semiconductor device 失效
标题翻译：高电压MIS晶体管和半导体器件
公开(公告)号：US5436486A
公开(公告)日：1995-07-25
申请号：US137355
申请日：1993-10-18
申请人： Naoto Fujishima , Akio Kitamura , Gen Tada
发明人： Naoto Fujishima , Akio Kitamura , Gen Tada
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/72 , H01L29/08
CPC分类号： H01L29/7393 , H01L29/1087
摘要： A high voltage MIS transistor includes a well region of a second conduction type formed by a step of injecting ions from the surface side of a semiconductor substrate of a first conduction type and a thermal diffusion step after the ion injecting step; an MIS part including a base layer of a first conduction type formed in one end portion of the well region, a base contact layer of a first conduction type which is formed in the base layer of a first conduction type and to which an emitter potential is applied, and a gate electrode provided so as to extend from an emitter layer of a second conduction type to the well region through an insulation gate film; and, a collector part including a base layer of a second conduction type formed in the other end portion of the well region, a collector layer of a first conduction type formed in the base layer of a second conduction type, and a high concentration contact layer of a first conduction type which is formed in the collector layer and to which a collector potential is applied.
摘要翻译：高电压MIS晶体管包括通过在离子注入步骤之后从第一导电类型的半导体衬底和热扩散步骤的表面侧注入离子的步骤形成的第二导电类型的阱区域; MIS部分，包括形成在阱区的一个端部中的第一导电类型的基极层，形成在第一导电类型的基极层中的第一导电类型的基极接触层，发射极电位为以及栅电极，其设置成通过绝缘栅膜从第二导电类型的发射极层延伸到阱区; 以及集电体部分，其包括形成在所述阱区的另一端部中的第二导电类型的基极层，形成在所述第二导电类型的基极层中的第一导电类型的集电极层和高浓度接触层的第一导电类型，其形成在集电极层中并且施加集电极电位。

10. 发明授权

US5612564A Semiconductor device with limiter diode 失效
标题翻译：具有限幅二极管的半导体器件
公开(公告)号：US5612564A
公开(公告)日：1997-03-18
申请号：US369772
申请日：1995-01-06
申请人： Naoto Fujishima , Gen Tada
发明人： Naoto Fujishima , Gen Tada
IPC分类号： H01L27/02 , H01L27/08 , H01L29/78 , H01L29/76 , H01L31/062
CPC分类号： H01L29/7816 , H01L27/0255 , H01L29/0878 , H01L29/7801 , H01L29/7809 , H01L29/7818
摘要： A semiconductor device with a metal-insulator-semiconductor transistor and a limiter or sacrifice diode has predetermined breakdown voltage and constant withstand voltage. The device includes a special well region underlying a drain portion or contacting an edge of a drain portion.
摘要翻译：具有金属 - 绝缘体 - 半导体晶体管和限制器或牺牲二极管的半导体器件具有预定的击穿电压和恒定的耐受电压。该装置包括在排水部分下面或接触排水部分的边缘的特殊井区域。

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