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1. 发明申请

US20050127439A1 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 有权
公开(公告)号：US20050127439A1
公开(公告)日：2005-06-16
申请号：US11030432
申请日：2005-01-06
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/266 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.

2. 发明授权

US07195980B2 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 有权
标题翻译：具有高击穿电压的半导体器件及其制造方法
公开(公告)号：US07195980B2
公开(公告)日：2007-03-27
申请号：US11030432
申请日：2005-01-06
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

3. 发明授权

US06740952B2 High withstand voltage semiconductor device 有权
标题翻译：高耐压半导体器件
公开(公告)号：US06740952B2
公开(公告)日：2004-05-25
申请号：US10096357
申请日：2002-03-12
申请人： Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L2358
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/404 , H01L29/41725 , H01L29/42368 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a stable high withstand voltage lateral MISFET device which suppresses a gradual withstand voltage drop under high voltage and humidity conditions. In a MISFET device with a 700V breakdown drain voltage, the length of extension Mc (&mgr;m) of a field plate FP1 from the source side end of a thermal oxidization film, and the total insulating film thickness Tox (&mgr;m) directly below the extending tip of the field plate FP1, are greater than or equal to lower limit values Mcmin, Tcmin. As a result, even if there is growth in charge accumulation at the interface of the mold resin, the field strength at a point B and point C is always lower than at a point A, which suppresses a gradual withstand voltage drop and a gradual ON current drop, whereby it becomes possible to realize a withstand voltage of 700V.
摘要翻译：半导体器件包括稳定的高耐压横向MISFET器件，其抑制在高电压和湿度条件下的逐渐耐受电压降。在具有700V击穿漏极电压的MISFET器件中，场板FP1的距离热氧化膜的源侧端的延伸长度Mc（母体）的长度以及在延伸尖端正下方的总绝缘膜厚度Tox（母体）的场板FP1大于或等于下限值Mcmin，Tcmin。结果，即使模具树脂的界面处的电荷累积增加，点B和点C的场强始终低于点A处的场强，这抑制了逐渐的耐压降和逐渐的导通电流下降，从而可以实现700V的耐受电压。

4. 发明授权

US06525390B2 MIS semiconductor device with low on resistance and high breakdown voltage 有权
标题翻译：具有低导通电阻和高击穿电压的MIS半导体器件
公开(公告)号：US06525390B2
公开(公告)日：2003-02-25
申请号：US09793833
申请日：2001-02-27
申请人： Gen Tada , Akio Kitamura , Masaru Saito , Naoto Fujishima
发明人： Gen Tada , Akio Kitamura , Masaru Saito , Naoto Fujishima
IPC分类号： H01L2972
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/405 , H01L29/7818 , H01L29/7835
摘要： The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering. The semiconductor device according to the invention includes a p-type highly resistive semiconductor substrate; an n-type offset region in the surface portion of the substrate; a p-type base region in the surface portion of the substrate, the base region including an n+-type source region in the surface portion thereof, the base region including a channel portion in the extended portion thereof extended between the source region and the n-type offset region; a p-type offset region in the surface portion of the n-type offset region, the potential of the p-type offset region being fixed at the source potential; an n+-type drain region in the surface portion of the n-type offset region; a field oxide film on the p-type offset region; a gate oxide film on the channel portion of the base region; a gate electrode on the gate oxide film; a source electrode on source region; a drain electrode on the drain region; an interlayer film; a protection film; and a spiral polysilicon thin film on the field oxide film, one end of the thin film being connected to the drain electrode, another end of the thin film being connected to the source electrode, the thin film being formed of pn-diodes connected in series.
摘要翻译：本发明提供一种以低制造成本制造的半导体器件，其防止击穿电压降低。根据本发明的半导体器件包括p型高电阻半导体衬底; 在衬底的表面部分中的n型偏移区域; 在基板的表面部分中的p型基极区域，所述基极区域在其表面部分包括n +型源极区域，所述基极区域包括在其延伸部分中的沟道部分在源区域和n 型偏移区域; 在n型偏移区域的表面部分中的p型偏移区域，p型偏移区域的电位固定在源极电位; n型偏移区域的表面部分中的n +型漏极区域; p型偏移区上的场氧化膜; 在所述基极区域的沟道部分上的栅氧化膜; 栅氧化膜上的栅电极; 源区上的源电极; 漏极区域上的漏电极; 中间膜; 保护膜; 以及场氧化膜上的螺旋状多晶硅薄膜，薄膜的一端与漏电极连接，薄膜的另一端与源电极连接，薄膜由串联连接的pn二极管形成。

5. 发明申请

US20070155144A1 SEMICONDUCTOR DEVICE EXHIBITING A HIGH BREAKDOWN VOLTAGE AND THE METHOD OF MANUFACTURING THE SAME 失效
标题翻译：展示高突变电压的半导体器件及其制造方法
公开(公告)号：US20070155144A1
公开(公告)日：2007-07-05
申请号：US11681525
申请日：2007-03-02
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/425
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

6. 发明授权

US06853034B2 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 失效
标题翻译：具有高击穿电压的半导体器件及其制造方法
公开(公告)号：US06853034B2
公开(公告)日：2005-02-08
申请号：US09756686
申请日：2001-01-09
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/266 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/76 , H01L23/58
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

7. 发明授权

US07687385B2 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same 失效
标题翻译：具有高击穿电压的半导体器件及其制造方法
公开(公告)号：US07687385B2
公开(公告)日：2010-03-30
申请号：US11681525
申请日：2007-03-02
申请人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
发明人： Kazuo Matsuzaki , Naoto Fujishima , Akio Kitamura , Gen Tada , Masaru Saito
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1079 , H01L29/41775 , H01L29/42368 , H01L29/66598 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.
摘要翻译：本发明提供了以低制造成本制造的稳定且高的击穿电压的半导体器件。本发明的半导体器件包括n型硅衬底; 在基板的表面部分中的p型基极区域; n型衬底的表面部分中的n型漏极区域; n型衬底的表面部分中的p型偏移区域; p型基极区域的表面部分中的n型源极区域; p型基极区域的表面部分中的p型接触区域; 位于p型基极区域的延伸部分之间的栅电极，其在n型源极区域和n型衬底（或p型偏移区域）之间延伸，栅极绝缘膜插入其间; 栅极电极和p型偏移区域上的绝缘膜; n型源极区上的源电极; 以及n型漏区上的漏电极。 p型偏移区域由第一p型子区域，第二p型子区域和第三p型子区域形成。

8. 发明授权

US06844598B2 Lateral high breakdown voltage MOSFET and device provided therewith 有权
标题翻译：横向高击穿电压MOSFET及其提供的装置
公开(公告)号：US06844598B2
公开(公告)日：2005-01-18
申请号：US10779790
申请日：2004-02-18
申请人： Gen Tada , Masaru Saito
发明人： Gen Tada , Masaru Saito
IPC分类号： H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78 , H01L23/62
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/42364 , H01L29/42368 , H01L2924/0002 , H01L2924/00
摘要： A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.
摘要翻译：第一导电类型的横向高击穿电压MOSFET的栅极氧化膜的膜厚形成为其中源极和漏极之间的绝对最大额定电压的电场值等于或小于4的厚度 MV / cm，并且形成漏极扩散层，使得其中杂质的总量变为等于或大于2×10 12 / cm 2，以降低横向高击穿电压MOSFET的导通电阻，同时确保并且降低横向高击穿电压MOSFET的面积。

9. 发明授权

US06818954B2 Lateral high breakdown voltage MOSFET and device provided therewith 有权
标题翻译：横向高击穿电压MOSFET及其提供的装置
公开(公告)号：US06818954B2
公开(公告)日：2004-11-16
申请号：US10308200
申请日：2002-12-03
申请人： Gen Tada , Masaru Saito
发明人： Gen Tada , Masaru Saito
IPC分类号： H01L2362
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/42364 , H01L29/42368 , H01L2924/0002 , H01L2924/00
摘要： A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuing a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.
摘要翻译：第一导电类型的横向高击穿电压MOSFET的栅极氧化膜的膜厚形成为其中源极和漏极之间的绝对最大额定电压的电场值等于或小于4的厚度 MV / cm，并且形成漏极扩散层，使得其中杂质的总量变为等于或大于2×10 12 / cm 2，以降低横向高击穿电压MOSFET的导通电阻，同时伴随着并且降低横向高击穿电压MOSFET的面积。

10. 发明授权

US08283705B2 Junction field effect transistor, integrated circuit for switching power supply, and switching power supply 有权
标题翻译：交流场效应晶体管，开关电源集成电路和开关电源
公开(公告)号：US08283705B2
公开(公告)日：2012-10-09
申请号：US13053884
申请日：2011-03-22
申请人： Masaru Saito , Koji Sonobe
发明人： Masaru Saito , Koji Sonobe
IPC分类号： H01L31/112
CPC分类号： H01L29/0692 , H01L27/098 , H01L29/1066 , H01L29/808 , H02M1/36
摘要： A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.
摘要翻译：开关电源具有启动电路，该启动电路包括场效应晶体管（JFET），场效应晶体管（JFET）具有形成在p型衬底的表面层中的栅极区域（p型阱区域）和漂移区域第一n型井区）。在漂移区域周围形成多个源极区域（第二n型阱区域）。漏极区（第三n型阱区）形成在源区的中央。漏极区域和源极区域可以同时形成。连接到源极区域的源电极布线的金属布线被分成至少两个组，以形成至少两个结场效应晶体管。

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