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1. 发明授权

US5654931A High-speed semiconductor memory device and data processing system using the same 失效
标题翻译：高速半导体存储器件和数据处理系统使用相同
公开(公告)号：US5654931A
公开(公告)日：1997-08-05
申请号：US213531
申请日：1994-03-16
申请人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
发明人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
IPC分类号： G11C7/22 , G11C13/00
CPC分类号： G11C7/22
摘要： A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved. Another feature is that either the input/output pads of the data into or out of the semiconductor integrated circuit device or their accompanying circuit units are distributed in the semiconductor integrated circuit device. The individual features described above can be used solely or in combination, if necessary, to achieve the above-specified objects.
摘要翻译：半导体集成电路器件被分成多个块，它们分别配备有信号生成单元，使得信号生成单元分布在半导体集成电路器件中。优选地，半导体集成电路器件被构造为在对数据和控制信号进行了所有初始逻辑运算之后，通过针对各个块提供的脉冲产生单元产生脉冲信号。由于这种结构，例如，SRAM可以将其写恢复时间最小化为0，从而可以实现高速操作。此外，由于为每个块提供预编码器，所以可以减少芯片中的布线数量和面积，以提高半导体集成电路器件的集成度。此外，芯片中的信号延迟和偏斜可以降低，从而可以实现高速度。另一个特征是将半导体集成电路器件的数据的输入/输出焊盘或其相应的电路单元分布在半导体集成电路器件中。如果需要，可以单独地或组合地使用上述各个特征来实现上述目的。

2. 发明授权

US5398318A High speed, low noise output buffer with non-identical pairs of output transistors 失效
标题翻译：具有不相同输出晶体管对的高速，低噪声输出缓冲器
公开(公告)号：US5398318A
公开(公告)日：1995-03-14
申请号：US608370
申请日：1990-11-02
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

3. 发明授权

US5680066A Signal transition detector circuit 失效
标题翻译：信号转换检测电路
公开(公告)号：US5680066A
公开(公告)日：1997-10-21
申请号：US182699
申请日：1994-01-13
申请人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira Ide , Masahiro Yamamura , Hideaki Uchida
发明人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira Ide , Masahiro Yamamura , Hideaki Uchida
IPC分类号： G11C7/10 , G11C8/06 , G11C8/10 , G11C8/18 , H03K5/1534 , H03K19/0175 , H03K5/153 , G01R29/02 , H03K3/033
CPC分类号： G11C7/1057 , G11C7/1051 , G11C8/06 , G11C8/10 , G11C8/18 , H03K19/017518 , H03K5/1534
摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要翻译：一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

4. 发明授权

US5387827A Semiconductor integrated circuit having logic gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5387827A
公开(公告)日：1995-02-07
申请号：US643372
申请日：1991-01-22
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , H03K19/23
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了一种半导体集成逻辑电路，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入信号的第一输入端，其中每个逻辑门耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。这种布置对于使用公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效。还提供了一种用于半导体存储器电路的改进的读/写布置，其包括在写入操作期间防止公共读取线连接到数据线的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

5. 发明授权

US5091883A Semiconductor memory and microprocessor 失效
标题翻译：半导体存储器和微处理器
公开(公告)号：US5091883A
公开(公告)日：1992-02-25
申请号：US552100
申请日：1990-07-13
申请人： Nozomu Matsuzaki , Takashi Akioka , Masahiro Iwamura , Atushi Hiraishi , Tatsumi Yamauchi , Yuji Yokoyama , Yutaka Kobayashi , Hideaki Uchida
发明人： Nozomu Matsuzaki , Takashi Akioka , Masahiro Iwamura , Atushi Hiraishi , Tatsumi Yamauchi , Yuji Yokoyama , Yutaka Kobayashi , Hideaki Uchida
IPC分类号： G11C11/41 , G11C5/06 , G11C11/401 , G11C11/409 , H01L27/10
CPC分类号： G11C5/063
摘要： An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.
摘要翻译：用于处理外部信号的输入缓冲器被提供在通路中的一个通道中，该通道最靠近用于将多个存储单元块的整体纵向或横向均匀地分成两部分的通道，该通道插入相邻的存储单元可以缩短输入缓冲器的经处理信号的多个存储单元块的块，从而可以缩短信号从输入缓冲器传递到存储单元块的每个存储单元的长度。因此，由于存储单元或者存在于输入缓冲器和存储单元之间的逻辑单元在没有时间延迟的情况下由几个失真的脉冲进行操作，所以可以减少访问时间并且可以提高微处理器的处理速度。此外，进一步提高了设计存储器或微处理器的系统的自由度。

6. 发明授权

US5787043A Semiconductor memory device having a redundancy capability 失效
标题翻译：具有冗余能力的半导体存储器件
公开(公告)号：US5787043A
公开(公告)日：1998-07-28
申请号：US394765
申请日：1995-02-27
申请人： Takashi Akioka , Yuji Yokoyama , Atsushi Hiraishi , Masahiro Iwamura , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Koichi Motohashi
发明人： Takashi Akioka , Yuji Yokoyama , Atsushi Hiraishi , Masahiro Iwamura , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Koichi Motohashi
IPC分类号： G11C29/00 , G11C11/401 , G11C29/04 , G11C7/00
CPC分类号： G11C29/844
摘要： A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.
摘要翻译：提供了一种半导体器件，其包括通过将存储器分成多个块形成的存储器衬垫和布置在每个存储器块块处的电路布置，用于至少对该块内的缺陷存储器单元产生访问抑制信号。使用这种布置，增加了用于消除缺陷的冗余存储单元阵列的访问速度，从而获得能够进行高速操作的半导体存储器件。

7. 发明授权

US5675548A Semiconductor integrated circuit having logi gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5675548A
公开(公告)日：1997-10-07
申请号：US608605
申请日：1996-02-29
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端信号，并且每个都耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

8. 发明授权

US5619151A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5619151A
公开(公告)日：1997-04-08
申请号：US473742
申请日：1995-06-07
申请人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira ide , Masahiro Yamamura , Hideaki Uchida
发明人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira ide , Masahiro Yamamura , Hideaki Uchida
IPC分类号： G11C7/10 , G11C8/06 , G11C8/10 , G11C8/18 , H03K5/1534 , H03K19/0175 , H03K5/153 , G01R29/02 , H03K3/033
CPC分类号： G11C7/1057 , G11C7/1051 , G11C8/06 , G11C8/10 , G11C8/18 , H03K19/017518 , H03K5/1534
摘要： A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要翻译：一种半导体存储器件，包括以下中的至少一个：（1）响应于输入地址产生内部地址信号的输入缓冲器电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据响应于ATD信号的时钟发生器的信号来控制器件的解码器，读出放大器和输出缓冲器。

9. 发明授权

US5544125A Semiconductor integrated circuit having logic gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5544125A
公开(公告)日：1996-08-06
申请号：US383866
申请日：1995-02-06
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端信号，并且每个都耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。还提供了一种改进的读/写布置，用于这样的半导体存储器电路，其包括在写入操作期间防止公共读取线与数据线连接的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

10. 发明授权

US5502820A Microprocessor having high speed, low noise output buffers 失效
标题翻译：微处理器具有高速，低噪声输出缓冲器
公开(公告)号：US5502820A
公开(公告)日：1996-03-26
申请号：US385656
申请日：1995-02-08
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

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