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    • 2. 发明授权
    • Digital-to-analog converter
    • 数模转换器
    • US06724333B1
    • 2004-04-20
    • US10148300
    • 2003-02-20
    • Masao NoroAkihiko Toda
    • Masao NoroAkihiko Toda
    • H03M166
    • H03M1/0619H03M1/687H03M1/745H03M1/765
    • There is provided a D/A converter that is free from a variation in the voltage width of 1 LSB between more significant bits and less significant bits of data for conversion due to variations in characteristics of resistors, transistors, etc. to thereby ensure a higher conversion accuracy than the conventional D/A converter. The eight more significant bits of 12-bit data for conversion are applied to a decoder 21, while the four less significant bits of the same are applied to a current addition circuit 22. The decoder 21 selects one of FET's F0 to F255 based on the eight more significant bits to cause one of voltages divided by a series circuit formed by resistors r0 to r255 to be applied to an operational amplifier 40. On the other hand, switches 30 to 33 of the current addition circuit 22 are switched, respectively, by the four less significant bits to turn respective FET's 35 to 38 on and off. As a result, currents flowing through turned-on ones of the FET's 35 to 38 are synthesized to flow through the resistor ra so that a voltage is generated across the resistor ra. The operational amplifier 40 synthesizes the two voltages and then outputs the synthesized voltage. An FET 24 and each of the FET's 35 to 38 form a current mirror circuit, whereby the influence of variations in characteristics of the resistors, etc. is eliminated.
    • 提供了一种D / A转换器,由于电阻器,晶体管等的特性的变化,在更高有效位之间不存在1LSB的电压宽度的变化和用于转换的较低有效位数据,从而确保更高的 转换精度比传统的D / A转换器。 用于转换的12位数据的八个更高有效位被应用于解码器21,而其相同的四个较低有效位被应用于当前的加法电路22.解码器21基于以下情况选择FET的F0至F255中的一个 八个更高有效位使得由电阻r0至r255形成的串联电路分压的一个电压施加到运算放大器40.另一方面,电流相加电路22的开关30至33分别切换为 将相应的FET 35打开和关闭的四个较低有效位。 结果,流过FET35至38中导通的电流的电流被合成以流过电阻器ra,使得跨过电阻器ra产生电压。 运算放大器40合成两个电压,然后输出合成电压。 FET24和FET35至38中的每一个形成电流镜电路,从而消除了电阻器等的变化的影响。
    • 3. 发明申请
    • D/A converter
    • D / A转换器
    • US20050007268A1
    • 2005-01-13
    • US10853896
    • 2004-05-26
    • Akihiko Toda
    • Akihiko Toda
    • H03M1/76H03M1/06H03M1/68H03M1/78
    • H03M1/0648H03M1/685H03M1/765
    • A D/A converter formed on a semiconductor substrate includes a plurality of resistance strings which are provided between a low voltage terminal and a high voltage terminal, each of the resistance strings including a plurality of resistances connected in series. The resistance strings to be connected at odd-numbered positions are arranged on the substrate in order of increasing in a direction from a near side of the terminal to which the low voltage is applied to the far side thereof, and the resistance strings to be connected at even-numbered positions are arranged on the substrate in order of increasing in a direction from the far side of the terminal to the near side. A voltage at a junction point of the resistances constituting the resistance string is selectively output in accordance with input data to be converted.
    • 形成在半导体基板上的D / A转换器包括设置在低电压端子和高电压端子之间的多个电阻串,每个电阻串包括串联连接的多个电阻。 要连接在奇数位置的电阻串按照从施加低电压的端子的近侧的方向向远离方向增加的顺序布置在基板上,并且要连接的电阻串 在偶数位置上,以从端子的远侧到近侧的方向增加的顺序排列在基板上。 根据要转换的输入数据选择性地输出构成电阻串的电阻的接合点处的电压。
    • 4. 发明授权
    • Circuit for shifting an input signal level including compensation for supply voltage variation
    • 用于移位输入信号电平的电路,包括电源电压变化的补偿
    • US06791392B2
    • 2004-09-14
    • US10253787
    • 2002-09-24
    • Toshio MaejimaAkihiko Toda
    • Toshio MaejimaAkihiko Toda
    • H03L500
    • H03K3/35613H03K3/012
    • A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).
    • 为基于不同电源电压(VDDL,VDDH)工作的不同电路系统提供信号电平移位电路,其中电源电压检测电路检测到关于输入信号(IN)的第一电源电压(VDDL)的减小。 电平移位电路包括由PMOS晶体管组成的负载电路部分和由NMOS晶体管组成的驱动电路部分,所有这些都被连接在一起以形成电流路径。 当在第一电源电压中检测到减小时,设置用于电流路径的开关电路打开,使得两个NMOS晶体管导通。 因此,可以有效地避免在电平移位电路中流过的电流的发生。 电平移位电路之后是触发器,触发器提供符合第二电源电压(VDDH)的输出信号(OUT)。
    • 7. 发明授权
    • Digital-to-analog converter utilizing MOS transistor switching circuit
with accompanying dummy gates to set same effective gate capacitance
    • 利用具有伴随的虚拟栅极的MOS晶体管开关电路来设置相同的有效栅极电容的数模转换器
    • US5894281A
    • 1999-04-13
    • US891121
    • 1997-07-10
    • Akihiko Toda
    • Akihiko Toda
    • H03M1/78H03M1/06H03M1/66
    • H03M1/0678H03M1/785
    • A digital-to-analog (D/A) converter provides superior linearity and reduces glitches by setting optimum dimensions for MOS transistors. The D/A converter is configured from a R-2R ladder circuit and a switching circuit. The R-2R ladder circuit consists of series resistors (R) and shunt resistors (2R), which are connected together at respective nodes corresponding to the bit stages. The switching circuit is configured from MOS transistors which are connected between reference potentials and the shunt resistors for each bit stage. The width/length (W/L) ratios of the MOS transistors are set such that the on-resistances of the transistors are sequentially increased by a factor of 2 in bit-stage descending order from the most significant bit (MSB) to the least significant bit (LSB) to maintain the linearity of the R-2R ladder circuit. Dummy gates are provided in parallel to the MOS transistors, except for the MOS transistors which correspond to the MSB, so that the same effective gate capacitance is set for each bit stage to provide uniform switching speed for each stage avoiding the occurrence of glitches.
    • 数模(D / A)转换器通过设置MOS晶体管的最佳尺寸,提供卓越的线性度并减少毛刺。 D / A转换器由R-2R梯形电路和开关电路构成。 R-2R梯形电路由串联电阻器(R)和分流电阻器(2R)组成,它们分别对应于位级的相应节点连接在一起。 开关电路由连接在每个位级的参考电位和分流电阻之间的MOS晶体管构成。 MOS晶体管的宽度/长度(W / L)比被设置为使得晶体管的导通电阻从最高有效位(MSB)到最低有效位(MSB)的比特级顺序依次增加2倍 有效位(LSB)来保持R-2R梯形电路的线性。 除了对应于MSB的MOS晶体管之外,与MOS晶体管并联设置虚拟栅极,使得针对每个位级设置相同的有效栅极电容,以为每个级提供均匀的开关速度,避免毛刺的发生。
    • 10. 发明授权
    • Digital-to-analog converter
    • 数模转换器
    • US5402127A
    • 1995-03-28
    • US75141
    • 1993-06-10
    • Akihiko Toda
    • Akihiko Toda
    • H01C13/02H03M1/06H03M1/76H03M1/78
    • H03M1/0646H03M1/765
    • A digital-to-analog converter (i.e., D/A converter) formed on a wafer comprises a decoder, transistors (e.g., field-effect transistors) and resistors. Since the wafer provides a gap between the p-well region and the n-well region, the resistance values of the resistors formed on the p-well region differ from those of the resistors formed on the n-well region. In order to cancel such difference between the resistance values, there are provided two series of resistors in parallel between a power-applying terminal and a ground terminal, wherein each of two series of resistors contain two kinds of resistors respectively formed on the p-well region and the n-well region, while a midpoint of the first series of resistors is connected with a midpoint of the second series of resistors. Due to the direct connection between two midpoints, the potential applied to these midpoints are stabilized and set at the certain fixed voltage. Thus, it is possible to obtain a desirable precision for the linear digital-to-analog conversion characteristic of the D/A converter, regardless of the difference between the resistance values of the resistors respectively formed on the p-well region and n-well region on the wafer.
    • 形成在晶片上的数模转换器(即,D / A转换器)包括解码器,晶体管(例如场效应晶体管)和电阻器。 由于晶片在p阱区域和n阱区域之间提供间隙,所以形成在p阱区域上的电阻器的电阻值与形成在n-阱区域上的电阻器的电阻值不同。 为了消除电阻值之间的差异,在功率施加端子和接地端子之间并联设置两个串联的电阻器,其中两个串联电阻器中的每一个包含分别形成在p阱上的两种电阻器 区域和n阱区域,而第一系列电阻器的中点与第二系列电阻器的中点连接。 由于两个中点之间的直接连接,施加到这些中点的电位被稳定并设置在一定的固定电压。 因此,可以获得D / A转换器的线性数/模转换特性的期望精度,而不管分别形成在p阱区和n阱上的电阻的电阻值之间的差异如何 晶圆上的区域。