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1. 发明申请

US20080104550A1 COMPENSATING FOR LAYOUT DIMENSION EFFECTS IN SEMICONDUCTOR DEVICE MODELING 失效
标题翻译：补偿半导体器件建模中的布局尺寸效应
公开(公告)号：US20080104550A1
公开(公告)日：2008-05-01
申请号：US11537390
申请日：2006-09-29
申请人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
发明人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.
摘要翻译：一种方法包括接收与集成电路装置相关联的设计数据。集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。基于经调整的尺寸模拟集成电路器件。

2. 发明授权

US07793240B2 Compensating for layout dimension effects in semiconductor device modeling 失效
标题翻译：补偿半导体器件建模中的布局尺寸效应
公开(公告)号：US07793240B2
公开(公告)日：2010-09-07
申请号：US11537390
申请日：2006-09-29
申请人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
发明人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.
摘要翻译：一种方法包括接收与集成电路装置相关联的设计数据。集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。基于经调整的尺寸模拟集成电路器件。

3. 发明申请

US20090090969A1 ELECTRONIC DEVICE AND METHOD OF BIASING 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US20090090969A1
公开(公告)日：2009-04-09
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

4. 发明申请

US20070298524A1 METHODS OF QUANTIFYING VARIATIONS RESULTING FROM MANUFACTURING-INDUCED CORNER ROUNDING OF VARIOUS FEATURES, AND STRUCTURES FOR TESTING SAME 有权
标题翻译：定量生成各种特征的角膜绕组变化量化方法及其测试结构
公开(公告)号：US20070298524A1
公开(公告)日：2007-12-27
申请号：US11425913
申请日：2006-06-22
申请人： DAVID D. WU , Mark W. Michael , Akif Sultan , Jingrong Zhou
发明人： DAVID D. WU , Mark W. Michael , Akif Sultan , Jingrong Zhou
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/34 , G03F7/70658 , H01L22/12
摘要： The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.
摘要翻译：本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果以确定制造性角落四舍五入对多个测试结构的性能的影响。

5. 发明授权

US07504270B2 Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same 有权
标题翻译：量化由各种特征的制造引起的角圆化引起的变化的方法以及用于测试相同的结构的方法
公开(公告)号：US07504270B2
公开(公告)日：2009-03-17
申请号：US11425913
申请日：2006-06-22
申请人： David D. Wu , Mark W. Michael , Akif Sultan , Jingrong Zhou
发明人： David D. Wu , Mark W. Michael , Akif Sultan , Jingrong Zhou
IPC分类号： G10R31/26 , H01L21/66
CPC分类号： H01L22/34 , G03F7/70658 , H01L22/12
摘要： The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.
摘要翻译：本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果以确定制造性角落四舍五入对多个测试结构的性能的影响。

6. 发明申请

US20120003802A1 TRANSISTOR WITH ASYMMETRIC SILICON GERMANIUM SOURCE REGION 有权
标题翻译：具有不对称硅锗源区的晶体管
公开(公告)号：US20120003802A1
公开(公告)日：2012-01-05
申请号：US13230083
申请日：2011-09-12
申请人： Jian Chen , James F. Buller , Akif Sultan
发明人： Jian Chen , James F. Buller , Akif Sultan
IPC分类号： H01L21/336
CPC分类号： H01L29/78618 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7848
摘要： The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
摘要翻译：本发明涉及具有不对称硅锗源区的晶体管及其制造方法。在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区基质。

7. 发明授权

US08035098B1 Transistor with asymmetric silicon germanium source region 有权
标题翻译：晶体管与不对称硅锗源区
公开(公告)号：US08035098B1
公开(公告)日：2011-10-11
申请号：US11278618
申请日：2006-04-04
申请人： Jian Chen , James F. Buller , Akif Sultan
发明人： Jian Chen , James F. Buller , Akif Sultan
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/78618 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7848
摘要： The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
摘要翻译：本发明涉及具有不对称硅锗源区的晶体管及其制造方法。在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区基质。

8. 发明授权

US08377781B2 Transistor with asymmetric silicon germanium source region 有权
标题翻译：晶体管与不对称硅锗源区
公开(公告)号：US08377781B2
公开(公告)日：2013-02-19
申请号：US13230083
申请日：2011-09-12
申请人： Jian Chen , James F. Buller , Akif Sultan
发明人： Jian Chen , James F. Buller , Akif Sultan
IPC分类号： H01L21/336
CPC分类号： H01L29/78618 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7848
摘要： The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
摘要翻译：本发明涉及具有不对称硅锗源区的晶体管及其制造方法。在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区基质。

9. 发明授权

US08687417B2 Electronic device and method of biasing 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US08687417B2
公开(公告)日：2014-04-01
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Akif Sultan , Fred Hause , Donna Michael
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Akif Sultan , Fred Hause
IPC分类号： G11C11/34 , G11C16/04 , G11C16/02 , G11C16/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

10. 发明授权

US06921704B1 Method for improving MOS mobility 有权
标题翻译：提高MOS迁移率的方法
公开(公告)号：US06921704B1
公开(公告)日：2005-07-26
申请号：US10700557
申请日：2003-11-05
申请人： David Wu , Akif Sultan , Bin Yu
发明人： David Wu , Akif Sultan , Bin Yu
IPC分类号： H01L21/762 , H01L21/764 , H01L21/8234 , H01L21/8238 , H01L21/76
CPC分类号： H01L21/764 , H01L21/76224 , H01L21/823481 , H01L21/823878
摘要： A method of forming a silicon-on-insulator semiconductor device including providing a substrate and forming a trench in the substrate, wherein the trench includes opposing side walls extending upwardly from a base of the trench. The method also includes depositing at least two insulating layers into the trench to form a shallow trench isolation structure, wherein an innermost of the insulating layers substantially conforms to the base and the two side walls of the trench and an outermost of the insulating layers spans the side walls of the trench so that a gap is formed between the insulating layers in the trench. The gap creates compressive forces within the shallow trench isolation structure, which in turn creates tensile stress within the surrounding substrate to enhance mobility of the device.
摘要翻译：一种形成绝缘体上半导体器件的方法，包括提供衬底并在衬底中形成沟槽，其中沟槽包括从沟槽的基底向上延伸的相对的侧壁。该方法还包括将至少两个绝缘层沉积到沟槽中以形成浅沟槽隔离结构，其中绝缘层的最内层基本上与基底一致并且沟槽的两个侧壁和绝缘层的最外层横跨沟槽的侧壁，使得在沟槽中的绝缘层之间形成间隙。间隙在浅沟槽隔离结构内产生压缩力，这反过来在周围的衬底内产生拉伸应力，以增强器件的移动性。

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