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1. 发明授权

US06295579B1 Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas 失效
标题翻译：并行处理器系统包括具有可独立寻址的本地和远程数据区的高速缓存存储器子系统
公开(公告)号：US06295579B1
公开(公告)日：2001-09-25
申请号：US09070851
申请日：1998-05-01
申请人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
发明人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0848 , G06F2212/272
摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.
摘要翻译：并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

2. 发明授权

US5778429A Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas 失效
标题翻译：并行处理器系统包括具有可独立寻址的本地和远程数据区的高速缓存存储器子系统
公开(公告)号：US5778429A
公开(公告)日：1998-07-07
申请号：US497751
申请日：1995-07-03
申请人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
发明人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
IPC分类号： G06F15/17 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0848 , G06F2212/272
摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.
摘要翻译：并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

3. 发明授权

US5898883A Memory access mechanism for a parallel processing computer system with distributed shared memory 失效
标题翻译：具有分布式共享存储器的并行处理计算机系统的存储器访问机制
公开(公告)号：US5898883A
公开(公告)日：1999-04-27
申请号：US368618
申请日：1995-01-04
申请人： Hiroaki Fujii , Toshiaki Tarui , Naonobu Sukegawa
发明人： Hiroaki Fujii , Toshiaki Tarui , Naonobu Sukegawa
IPC分类号： G06F15/17 , G06F12/02 , G06F15/16
CPC分类号： G06F12/0284
摘要： To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.
摘要翻译：为了增加整个并行处理计算机系统的可用存储器的容量并有效地利用地址空间而不浪费，可变长度的全局/局部分配字段被提供在固定长度的地址中。当本地设置该字段时，该地址被用作本地处理器引用的本地存储器区域的地址。当分配被全局设置时，剩余地址是可变长度的逻辑处理器号码（该数字被转换成物理处理器号码）和可变长度偏移地址，用于指定属于全局区域中的处理器的全局存储器区域一组处理器的存储器，该组的所有处理器可以引用全局存储器。存储器访问接口执行对本地处理器的存储器的本地或全局区域或另一处理器的存储器的全局区域的存储器访问。

4. 发明授权

US5606686A Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor 失效
标题翻译：基于在将数据读取到处理器之后存储在存储器中的数据的存储位置的目录，在多处理器中的共享主存储器的访问控制方法
公开(公告)号：US5606686A
公开(公告)日：1997-02-25
申请号：US328759
申请日：1994-10-24
申请人： Toshiaki Tarui , Naonobu Sukegawa , Hiroaki Fujii , Katsuyoshi Kitai
发明人： Toshiaki Tarui , Naonobu Sukegawa , Hiroaki Fujii , Katsuyoshi Kitai
IPC分类号： G06F15/17 , G06F12/08 , G06F15/173
CPC分类号： G06F12/0817 , G06F12/0813 , G06F15/17393 , G06F2212/2542
摘要： A main memory shared by plural processing units in a parallel computer system is composed of plural partial main memories. A directory for each data line of the main memory is generated after the data line has been cached in one of the processing units. The directory is held in one of the partial main memories in place of the data line. The directory indicates a processing unit which has cached the data line. A status bit C provided for the data line is set. If a subsequent read request is given to the data line, the status C bit is checked and the directory is used to identify a processing unit that has cached the data line. The request is transferred to the identified processing unit, and the data line is transferred from that processing unit to the processing unit that has issued the request. If a processing unit that has cached the data line has replaced the data line, it is checked if there is a processing unit that has cached the data line. If there is none, the data line is written back into the one partial main memory. If there is, the data line is not written back. Another status bit RO is also used for each data line. It indicates if the data line is read only. If a data line is read only, generation of the directory and storing it in the partial main memory is prohibited.
摘要翻译：并行计算机系统中的多个处理单元共享的主存储器由多个部分主存储器构成。在数据线已被缓存在一个处理单元中之后，生成主存储器的每条数据线的目录。该目录被保存在一部分主存储器中以代替数据线。该目录指示已经缓存数据线的处理单元。设置为数据线提供的状态位C。如果向数据线提供后续的读取请求，则检查状态C位，并使用该目录来标识缓存数据线的处理单元。该请求被传送到所识别的处理单元，并且数据线从该处理单元传送到已经发出请求的处理单元。如果缓存数据线的处理单元已经取代了数据线，则检查是否存在缓存数据行的处理单元。如果没有，则数据线被写回到一个部分主存储器中。如果有，数据行不会被写回。每个数据线也使用另一个状态位RO。它指示数据行是否为只读。如果数据线是只读的，则禁止生成目录并将其存储在部分主存储器中。

5. 发明授权

US6119150A Message passing distributed shared memory system that eliminates unnecessary software controlled cache flushes or purges 失效
标题翻译：消息传递分布式共享内存系统，消除了不必要的软件控制的缓存刷新或清除
公开(公告)号：US6119150A
公开(公告)日：2000-09-12
申请号：US789184
申请日：1997-01-24
申请人： Hiroaki Fujii , Tadaaki Isobe , Makoto Koga , Hideya Akashi
发明人： Hiroaki Fujii , Tadaaki Isobe , Makoto Koga , Hideya Akashi
IPC分类号： G06F15/17 , G06F12/08 , G06F15/167 , G06F13/00
CPC分类号： G06F12/0837 , G06F12/0813
摘要： An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.
摘要翻译：采用根据来自存储控制器的请求执行高速缓存一致性控制的指令处理器。存储控制器设置有高速缓存一致性控制处理电路，其对作为通过数据传送发生的主存储器访问的目的地的地址执行高速缓存一致性控制。同时，高速缓存一致性控制处理电路在数据传送过程中对每条高速缓存线执行一次高速缓存一致性控制处理。消除了与数据传输有关的软件执行的高速缓存一致性控制处理，提高了包括缓存存储器控制在内的数据传输效率，并减少了对程序的限制。

6. 发明授权

US09277667B2 Display 有权
公开(公告)号：US09277667B2
公开(公告)日：2016-03-01
申请号：US14118051
申请日：2012-05-24
申请人： Hiroaki Fujii , Satoshi Mukoyama , Soya Araki , Hisanori Tsuboi , Hidetomo Miyake , Takeshi Yamamoto
发明人： Hiroaki Fujii , Satoshi Mukoyama , Soya Araki , Hisanori Tsuboi , Hidetomo Miyake , Takeshi Yamamoto
IPC分类号： H05K7/02 , F21V8/00 , G09F9/30 , G02F1/1333 , G02F1/1335
CPC分类号： G02F1/133308 , F21V11/00 , G02B6/0011 , G02B6/0041 , G02B6/0088 , G02B6/0093 , G02F1/133514 , G02F1/133528 , G02F1/133608 , G02F1/13439 , G02F1/1368 , G02F1/137 , G02F2001/133302 , G02F2001/133314 , G02F2001/13332 , G02F2001/13712 , G02F2201/123 , G09F9/30 , H05B33/22 , H05K5/0017 , H05K5/02 , H05K7/023 , H05K7/1427
摘要： A display which thickness is allowed to be reduced is provided. A display includes: a display panel; and a back-face member having rigidity and provided on a back face of the display panel, the back-face member covering the back face, or the back face and other part of the display panel.

7. 发明授权

US08767320B2 Endoscope optical system and endoscope 有权
标题翻译：内镜光学系统和内窥镜
公开(公告)号：US08767320B2
公开(公告)日：2014-07-01
申请号：US13984169
申请日：2012-02-07
申请人： Hiroaki Fujii
发明人： Hiroaki Fujii
IPC分类号： G02B21/02 , G02B13/04 , G02B9/34 , G02B23/24
CPC分类号： G02B23/243 , A61B1/00163 , A61B1/00174 , G02B9/34 , G02B13/0015 , G02B13/04 , G02B23/2423 , G02B23/2438
摘要： An endoscope optical system, including a front group and a rear group arranged in this order from an object side such that an aperture stop is arranged between the front and rear groups, wherein the front group includes a negative lens and a positive lens arranged in this order from the object side, the rear group includes a positive lens and a cemented lens arranged in this order from the object side, and when f (unit: mm) denotes a focal length of an entire endoscope optical system, EX (unit: mm) denotes a distance (which takes a minus sign on the object side with respect to an image plane) from the image plane to an exit pupil, and f2 (unit: mm) denotes a focal length of the rear group, the endoscope optical system satisfies conditions: −10
摘要翻译：一种内窥镜光学系统，包括从物体侧依次排列的前组和后组，使得前组和后组之间布置孔径光阑，其中前组包括负透镜和布置在该组中的正透镜从物体侧起，后组包括从物体侧依次排列的正透镜和胶合透镜，并且当f（单位：mm）表示整个内窥镜光学系统的焦距时，EX（单位：mm ）表示从图像平面到出射光瞳的距离（相对于像面在物体侧取负号），f2（单位：mm）表示后组的焦距，内窥镜光学系统满足条件：-10

8. 发明申请

US20130019451A1 POLYAMIDE RESIN COMPOSITION FOR SLIDING PART, SLIDING PART, AND METHOD FOR PRODUCING A SLIDING PART AS WELL AS METHOD FOR PRODUCING AN AUTOMOBILE 审中-公开
标题翻译：用于滑动部件，滑动部件的聚酰胺树脂组合物以及用于生产滑动部件的方法以及用于生产汽车的方法
公开(公告)号：US20130019451A1
公开(公告)日：2013-01-24
申请号：US13637511
申请日：2011-03-23
申请人： Shigekazu Okamura , Hiroaki Fujii
发明人： Shigekazu Okamura , Hiroaki Fujii
IPC分类号： C08L77/06 , C08K7/14 , B23P11/00
CPC分类号： C08L77/00 , B29C45/0001 , B29K2077/00 , C08K7/14 , C08L25/06 , C08L53/02 , F16H55/06 , Y10T29/49826
摘要： A polyamide resin composition for sliding part and a sliding part, each being prevented from shrinking both in the MD direction and in the TD direction (having excellent dimensional stability as well as excellent dimensional stability when water is absorbed into the resin) and having excellent impact resistance, a method for producing the sliding part, and a method for producing an automobile using the sliding part. The polyamide resin composition for sliding part includes a polyamide resin (component A) and a styrene polymer (component B), wherein the component B has a deflection temperature under load of 140 to 280° C., and the weight ratio of the component A to the component B (A/B) is 95/5 to 77/23.
摘要翻译：一种用于滑动部件和滑动部件的聚酰胺树脂组合物各自被防止在MD方向和TD方向上收缩（当水被吸收到树脂中时具有优异的尺寸稳定性以及优异的尺寸稳定性）并且具有优异的冲击电阻，滑动部的制造方法以及使用该滑动部的汽车的制造方法。用于滑动部件的聚酰胺树脂组合物包括聚酰胺树脂（组分A）和苯乙烯聚合物（组分B），其中组分B的负载挠曲温度为140〜280℃，组分A 对组分B（A / B）为95/5至77/23。

9. 发明申请

US20120299809A1 DISPLAY 有权
标题翻译：显示
公开(公告)号：US20120299809A1
公开(公告)日：2012-11-29
申请号：US13463922
申请日：2012-05-04
申请人： Hiroaki Fujii , Satoshi Mukoyama , Soya Araki , Hisanori Tsuboi , Hidetomo Miyake
发明人： Hiroaki Fujii , Satoshi Mukoyama , Soya Araki , Hisanori Tsuboi , Hidetomo Miyake
IPC分类号： G09G3/36 , H05K7/00
CPC分类号： G02F1/133308 , G02F1/133615 , G02F2001/133314 , G02F2001/13332 , G02F2001/133331 , G02F2201/46 , G02F2202/28
摘要： A display includes: a display panel; a front-face member being provided on a front face of the display panel, and the front-face member covering a surrounding section, or the surrounding section and other part of the display panel; and a back-face member having rigidity and being provided on a back face of the display panel, the back-face member covering the back face, or the back face and other part of the display panel.
摘要翻译：显示器包括：显示面板; 前表面构件设置在所述显示面板的前表面上，所述前面构件覆盖所述显示面板的周围部分或周围部分和其他部分; 以及具有刚性的背面构件，设置在显示面板的背面，背面构件覆盖显示面板的背面或背面等。

10. 发明申请

US20110141697A1 DISPLAY APPARATUS (amended 有权
标题翻译：显示设备（修改
公开(公告)号：US20110141697A1
公开(公告)日：2011-06-16
申请号：US13059067
申请日：2009-08-26
申请人： Hiroaki Fujii , Shinpei Nagatani
发明人： Hiroaki Fujii , Shinpei Nagatani
IPC分类号： H05K7/20
CPC分类号： G02F1/133382 , G02B6/0051 , G02B6/0085 , G02F1/133308 , G02F1/133528 , G02F1/1339 , G02F2001/133302 , G02F2001/133314 , G02F2001/133317 , G02F2001/13332 , G02F2001/133628 , H05K7/20
摘要： Provided is a display apparatus including a display panel for displaying an image, a heat source arranged at a side surface of at least one side of the display panel, a heat absorbing section for absorbing heat generated by the heat source, a back surface plate arranged at a back surface side of the display panel and made of a metal, a portion of the back surface plate being in close contact with the heat absorbing section, a front surface plate arranged at a front surface side of the display panel and made of a metal, and a middle chassis arranged between the front surface plate and the heat absorbing section.
摘要翻译：本发明提供一种显示装置，包括显示图像的显示面板，布置在显示面板的至少一侧的侧面的热源，吸热部，其吸收由热源产生的热量;背面板，在显示面板的背面侧，由金属构成的背面板的一部分与吸热部紧密接触，前表面板配置在显示面板的前表面侧，金属和布置在前表面板和吸热部之间的中间框架。

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