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1. 发明申请

US20140380027A1 ELAPSED CYCLE TIMER IN LAST BRANCH RECORDS 有权
标题翻译：最近分支记录中的ELAPSED循环定时器
公开(公告)号：US20140380027A1
公开(公告)日：2014-12-25
申请号：US13922421
申请日：2013-06-20
申请人： Ahmad Yasin , Michael W. Chynoweth , Ofer Levy , Jason W. Brandt , Angela Schmid
发明人： Ahmad Yasin , Michael W. Chynoweth , Ofer Levy , Jason W. Brandt , Angela Schmid
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/30098 , G06F11/3419 , G06F11/348 , G06F2201/865 , G06F2201/88
摘要： A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.
摘要翻译：公开了一种在最后的分支记录（LBR）中实现经过周期定时器的处理装置。本公开的处理装置包括与处理装置的每个周期重复的最后一个分支记录（LBR）计数器和可通信地耦合到LBR计数器的LBR结构。 LBR结构包括多个LBR条目。此外，多个LBR条目的LBR条目包括由处理装置执行的分支指令的地址指令指针（IP），分支指令的目标的地址IP以及存储分支指令的值的经过时间字段当创建LBR条目时，LBR计数器。

2. 发明申请

US20150347267A1 Monitoring Performance of a Processing Device to Manage Non-Precise Events 有权
标题翻译：监控处理设备管理非精确事件的性能
公开(公告)号：US20150347267A1
公开(公告)日：2015-12-03
申请号：US14292140
申请日：2014-05-30
申请人： Jonathan D. Combs , Michael W. Chynoweth , Jason W. Brandt , Corey D. Gough
发明人： Jonathan D. Combs , Michael W. Chynoweth , Jason W. Brandt , Corey D. Gough
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F11/348 , G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to increment upon occurrence of a non-precise event in the processing device. The processing device also includes a precise event based sampling (PEBS) enable control communicably coupled to the performance counter. The processing device also includes a PEBS handler to generate and store a PEBS record including an architectural metadata defining a state of the processing device at a time of generation of the PEBS record. The processing device further includes a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS control and the PEBS handler. The NPEBS module causes the PEBS handler to generate the PEBS record for the non-precise event upon overflow of the performance counter.
摘要翻译：根据本文公开的实施例，提供了用于监视处理设备的管理非精确事件的性能的系统和方法。处理装置包括在处理装置中出现非精确事件时增加的性能计数器。处理设备还包括可通信地耦合到性能计数器的精确的基于事件的采样（PEBS）使能控制。处理设备还包括PEBS处理器，用于生成和存储包括在生成PEBS记录时定义处理设备的状态的架构元数据的PEBS记录。处理设备还包括可通信地耦合到PEBS控制和PEBS处理器的非精确事件采样（NPEBS）模块。 NPEBS模块使PEBS处理程序在性能计数器溢出时为非精确事件生成PEBS记录。

3. 发明申请

US20140189314A1 Real Time Instruction Trace Processors, Methods, and Systems 有权
标题翻译：实时指令跟踪处理器，方法和系统
公开(公告)号：US20140189314A1
公开(公告)日：2014-07-03
申请号：US13730834
申请日：2012-12-29
申请人： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
发明人： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
摘要： A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
摘要翻译：一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。还公开了其它方法，装置和系统。

4. 发明申请

US20140344552A1 PROVIDING STATUS OF A PROCESSING DEVICE WITH PERIODIC SYNCHRONIZATION POINT IN INSTRUCTION TRACING SYSTEM 有权
标题翻译：在指令跟踪系统中提供具有定期同步点的处理设备的状态
公开(公告)号：US20140344552A1
公开(公告)日：2014-11-20
申请号：US13895595
申请日：2013-05-16
申请人： Frank Binns , Matthew C. Merten , Mayank Bomb , Beeman C. Strong , Peter Lachner , Jason W. Brandt , Itamar Kazachinsky , Ofer Levy , MD A. Rahman
发明人： Frank Binns , Matthew C. Merten , Mayank Bomb , Beeman C. Strong , Peter Lachner , Jason W. Brandt , Itamar Kazachinsky , Ofer Levy , MD A. Rahman
IPC分类号： G06F9/30
CPC分类号： G06F11/3636 , G06F11/3024 , G06F11/3055 , G06F11/3476 , G06F11/348 , G06F2201/865
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.
摘要翻译：根据本文公开的实施例，提供了用于在指令跟踪系统中提供具有周期性同步点的处理设备的状态的系统和方法。例如，该方法可以包括基于分组日志中的唯一字节模式生成边界分组。边界包提供了分组解码的起始点。该方法还可以包括基于处理器的状态信息生成多个状态分组。当输出到分组日志中时，多个状态分组遵循边界分组。

5. 发明申请

US20210382987A1 PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS 有权
公开(公告)号：US20210382987A1
公开(公告)日：2021-12-09
申请号：US17407035
申请日：2021-08-19
申请人： Vedvyas Shanbhogue , Jason W. Brandt , Ravi L. Sahita , Barry E. Huntley , Baiju V. Patel , Deepak K. Gupta
发明人： Vedvyas Shanbhogue , Jason W. Brandt , Ravi L. Sahita , Barry E. Huntley , Baiju V. Patel , Deepak K. Gupta
IPC分类号： G06F21/52 , G06F3/06 , G06F12/14 , G06F9/30 , G06F9/46
摘要： A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

6. 发明授权

US10671547B2 Lightweight trusted tasks 审中-公开
公开(公告)号：US10671547B2
公开(公告)日：2020-06-02
申请号：US15384267
申请日：2016-12-19
申请人： Patrick Koeberl , Steffen Schulz , Vedvyas Shanbhogue , Jason W. Brandt , Venkateswara R. Madduri , Sang W. Kim , Julien Carreno
发明人： Patrick Koeberl , Steffen Schulz , Vedvyas Shanbhogue , Jason W. Brandt , Venkateswara R. Madduri , Sang W. Kim , Julien Carreno
IPC分类号： G06F12/14 , G06F21/74 , G06F21/57 , G06F9/4401
摘要： Methods and apparatus relating to lightweight trusted tasks are disclosed. In one embodiment, a processor includes a memory interface to a memory to store code, data, and stack segments for a lightweight-trusted task (LTT) mode task and for another task, a LTT control and status register including a lock bit, a processor core to enable LTT-mode, configure the LTT-mode task, and lock down the configuration by writing the lock bit, and a memory protection circuit to: receive a memory access request from the memory interface, the memory access request being associated with the other task, determine whether the memory access request is attempting to access a protected memory region of the LTT-mode task, and protect against the memory access request accessing the protected memory region of the LTT-mode task, regardless of a privilege level of the other task, and regardless of whether the other task is also a LTT-mode task.

7. 发明申请

US20200004959A1 MICROARCHITECTURAL MECHANISMS FOR THE PREVENTION OF SIDE-CHANNEL ATTACKS 审中-公开
公开(公告)号：US20200004959A1
公开(公告)日：2020-01-02
申请号：US16456578
申请日：2019-06-28
申请人： Robert S. Chappell , Jared W. STARK, IV , Joseph Nuzman , Stephen Robinson , Jason W. Brandt
发明人： Robert S. Chappell , Jared W. STARK, IV , Joseph Nuzman , Stephen Robinson , Jason W. Brandt
IPC分类号： G06F21/55 , G06F21/62 , G06F9/48 , G06F9/30 , G06F12/0802
摘要： Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

8. 发明授权

US10114651B2 Gathering and scattering multiple data elements 有权
公开(公告)号：US10114651B2
公开(公告)日：2018-10-30
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/00 , G06F12/08 , G06F9/38 , G06F9/30
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

9. 发明申请

US20180129506A1 GATHERING AND SCATTERING MULTIPLE DATA ELEMENTS 审中-公开
公开(公告)号：US20180129506A1
公开(公告)日：2018-05-10
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

10. 发明授权

US09804852B2 Conditional execution support for ISA instructions using prefixes 有权
公开(公告)号：US09804852B2
公开(公告)日：2017-10-31
申请号：US13976230
申请日：2011-11-30
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30072 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.

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