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1. 发明授权

US07920366B2 ESD configuration for low parasitic capacitance I/O 有权
标题翻译： ESD配置用于低寄生电容I / O
公开(公告)号：US07920366B2
公开(公告)日：2011-04-05
申请号：US12393417
申请日：2009-02-26
申请人： Chun-Ying Chen , Agnes Neves Woo
发明人： Chun-Ying Chen , Agnes Neves Woo
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.
摘要翻译：集成电路可以包括I / O焊盘，内部电路，电感器，静电放电（ESD）保护电路和ESD钳位。内部电路可以用第一电压源和第二电压源进行偏置，其中内部电路在第一节点处连接到I / O焊盘。 ESD保护电路可以连接在第一节点和第二节点之间。电感器可以连接在第二节点和第三电压源之间。此外，ESD钳位可以连接在第二节点和第二电压源之间。

2. 发明授权

US07505238B2 ESD configuration for low parasitic capacitance I/O 失效
标题翻译： ESD配置用于低寄生电容I / O
公开(公告)号：US07505238B2
公开(公告)日：2009-03-17
申请号：US11174731
申请日：2005-07-06
申请人： Agnes Neves Woo , Chun-Ying Chen
发明人： Agnes Neves Woo , Chun-Ying Chen
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An I/O ESD protection configuration of an integrated circuit that includes an ESD protection circuit connected between an I/O pad and an internal circuit at a first node and to an inductor at a second node. The inductor is connected between the second node and an external power supply. The external power supply provides a high reverse bias voltage across a diode of the ESD protection circuit. An ESD clamp is connected between the second node and a ground. An ESD discharge current is shunted through the ESD protection circuit and through the ESD clamp during a positive I/O ESD event. The inductor can be chosen to tune out a parasitic capacitance of the ESD clamp. The inductor can also block high frequency signals between the I/O pad and the external power supply, thereby minimizing the parasitic capacitance of the diode of the ESD protection circuit at high frequency.
摘要翻译：集成电路的I / O ESD保护配置，其包括连接在第一节点处的I / O焊盘和内部电路之间的ESD保护电路以及第二节点处的电感器。电感器连接在第二节点和外部电源之间。外部电源在ESD保护电路的二极管上提供高反向偏置电压。 ESD钳位器连接在第二节点和地之间。在正I / O ESD事件期间，ESD放电电流通过ESD保护电路并通过ESD钳位分流。可以选择电感来调整ESD钳位的寄生电容。电感器还可以阻挡I / O焊盘和外部电源之间的高频信号，从而最大限度地降低ESD保护电路在高频下的二极管的寄生电容。

3. 发明授权

US08717209B2 Successive equalizer for analog-to-digital converter (ADC) error correction 有权
标题翻译：用于模数转换器（ADC）误差校正的连续均衡器
公开(公告)号：US08717209B2
公开(公告)日：2014-05-06
申请号：US13604184
申请日：2012-09-05
申请人： Jiangfeng Wu , Tianwei Li , Wenbo Liu , Wei-Ta Shih , Chun-Ying Chen , Lin He , Randall Perlow , Binning Chen , Ramon Gomez
发明人： Jiangfeng Wu , Tianwei Li , Wenbo Liu , Wei-Ta Shih , Chun-Ying Chen , Lin He , Randall Perlow , Binning Chen , Ramon Gomez
IPC分类号： H03M1/06
CPC分类号： H03M1/0626 , H03M1/0614 , H03M1/44
摘要： Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.
摘要翻译：公开了各种流水线ADC，其基本上补偿由流水线ADC的各种ADC模块的缺陷导致的干扰或失真。流水线ADC包括各种ADC级以及耦合到各个ADC级的各种补偿级。各个ADC级将其相应的模拟输入从模拟信号域转换为数字信号域，以向后续ADC级提供各种数字输出信号和各种模拟残留信号。各种补偿级补偿由于先前ADC阶段的缺陷而导致的各种模拟残差信号的干扰或失真。

4. 发明授权

US07898314B2 Offset compensation using non-uniform calibration 有权
标题翻译：使用非均匀校准进行偏移补偿
公开(公告)号：US07898314B2
公开(公告)日：2011-03-01
申请号：US12385259
申请日：2009-04-02
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： H03L5/00
CPC分类号： H03M1/1019 , H03M1/12
摘要： Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.
摘要翻译：提供了使用校准进行偏移补偿的方法和系统。实施例使用不均匀校准的偏移补偿。实施例使得可以根据随机偏移的概率分布函数（PDF）配置校准方案。实施例使得可以根据随机偏移的PDF配置多个校准分辨率的校准方案。实施例使得可以根据随机偏移的PDF配置具有多个校准步骤值的校准方案。实施例可以针对各种类型的随机偏移来实现，包括但不限于高斯，伯努利，均匀，奇异，指数，伽马和帕累托分布偏移。

5. 发明授权

US07696704B2 Discharge lamp driving device and electronic device using the same 失效
标题翻译：放电灯驱动装置及使用其的电子装置
公开(公告)号：US07696704B2
公开(公告)日：2010-04-13
申请号：US11936767
申请日：2007-11-07
申请人： Chih-Chan Ger , Chun-Ying Chen
发明人： Chih-Chan Ger , Chun-Ying Chen
IPC分类号： H05B37/00
CPC分类号： H05B41/282 , Y02B20/183
摘要： A driving device for driving plural discharge lamps. A controller circuit converts a received signal to a first high voltage signal and a second high voltage signal. A first balancing circuit is mounted on a first connecting board and connected to one ends of the discharge lamps. A second balancing circuit is mounted on a second connecting board and connected to the other ends of the discharge lamps. A first set of high voltage lines connects the controller board and the first connecting board, and the first high voltage signal is outputted from the control circuit to the first balancing circuit via the first set of high voltage lines. A second set of high voltage lines connects the controller board and the second connecting board, and the second high voltage signal is outputted from the control circuit to the second balancing circuit via the second set of high voltage lines.
摘要翻译：一种用于驱动多个放电灯的驱动装置。控制器电路将接收到的信号转换为第一高电压信号和第二高电压信号。第一平衡电路安装在第一连接板上并连接到放电灯的一端。第二平衡电路安装在第二连接板上并连接到放电灯的另一端。第一组高压线路连接控制器板和第一连接板，并且第一高压信号经由第一组高压线从控制电路输出到第一平衡电路。第二组高压线路连接控制器板和第二连接板，第二高压信号经由第二组高压线从控制电路输出到第二平衡电路。

6. 发明申请

US20090251326A1 LOW POWER WARNING IN A PORTABLE COMMUNICATION DEVICE BASED ON PREDICTED DEVICE UTILIZATION 有权
标题翻译：基于预测设备利用的便携式通信设备中的低功率警告
公开(公告)号：US20090251326A1
公开(公告)日：2009-10-08
申请号：US12484430
申请日：2009-06-15
申请人： Neil Y. Kim , Pieter Vorenkamp , Sumant Ranganathan , Chun-Ying Chen
发明人： Neil Y. Kim , Pieter Vorenkamp , Sumant Ranganathan , Chun-Ying Chen
IPC分类号： G08B21/00
CPC分类号： H02J7/0047 , H04M1/72519 , H04W52/0258 , Y02D70/00
摘要： A system and method for providing a low power warning in a portable communication device based on predicted device utilization. Various aspects of the present invention may comprise monitoring power utilization for a portable communication device. A power utilization profile may be determined based, at least in part, on the results of the power utilization monitoring. Power availability for the portable communication device may be determined. Future power need for the portable communication device may be predicted based, at least in part, on the determined power utilization profile. The predicted future power need and the determined power availability may be analyzed to determine whether to generate a warning indicating a potential future power shortage. If it is determined that a potential future power shortage warning should be generated, such a warning may be generated. Such a warning may, for example, be generated in accordance with user specifications.
摘要翻译：一种用于基于预测的设备利用率在便携式通信设备中提供低功率警告的系统和方法。本发明的各个方面可以包括监视便携式通信设备的功率利用。可以至少部分地基于功率利用率监测的结果来确定功率利用率曲线。可以确定便携式通信设备的功率可用性。可以至少部分地基于确定的功率利用率曲线来预测便携式通信设备的未来功率需求。可以分析预测的未来功率需求和确定的功率可用性，以确定是否产生指示潜在的未来电力短缺的警告。如果确定应该产生潜在的未来电力短缺警告，则可能产生这种警告。这样的警告可以例如根据用户规格生成。

7. 发明授权

US07525366B2 Offset compensation using non-uniform calibration 失效
公开(公告)号：US07525366B2
公开(公告)日：2009-04-28
申请号：US11819676
申请日：2007-06-28
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： H03L5/00
CPC分类号： H03M1/1019 , H03M1/12
摘要： Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

8. 发明授权

US07394310B2 System and method for programmable switching characteristics of an analog switch in a transconductance amplifier 有权
标题翻译：跨导放大器中模拟开关的可编程开关特性的系统和方法
公开(公告)号：US07394310B2
公开(公告)日：2008-07-01
申请号：US10975105
申请日：2004-10-28
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： G06G7/26
CPC分类号： H03F3/45179 , H03F3/45197 , H03F3/45982 , H03F2203/45506
摘要： Provided are a method and system for controlling impedance in a transconductance amplifier. A system includes a first transconductance amplifier and a second transconductance amplifier configured to control electrical characteristics associated with the first transconductance amplifier. An operational amplifier is provided and has at least one input port connected to the second transconductance amplifier. Also included is a first digital to analog converter (DAC) connected to receive a current signal from the operational amplifier.
摘要翻译：提供了用于控制跨导放大器中的阻抗的方法和系统。一种系统包括第一跨导放大器和配置成控制与第一跨导放大器相关联的电特性的第二跨导放大器。提供一个运算放大器，并具有连接到第二跨导放大器的至少一个输入端口。还包括一个第一个数模转换器（DAC），用于接收来自运算放大器的电流信号。

9. 发明申请

US20070194771A1 Power management unit for use in portable applications 有权
标题翻译：用于便携式应用的电源管理单元
公开(公告)号：US20070194771A1
公开(公告)日：2007-08-23
申请号：US11790036
申请日：2007-04-23
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： G05F3/20
CPC分类号： G05F1/56 , G05F1/575
摘要： A voltage regulator includes a first stage capable of receiving a reference voltage and capable of having a first current flowing through the first stage. A second stage is capable of having a second current flowing through the second stage. A third stage is capable of outputting an output voltage and capable of having a third current flowing through the second stage. The first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and maximum output current. The first stage drives the second stage as a low input impedance load.
摘要翻译：电压调节器包括能够接收参考电压并能够具有流过第一级的第一电流的第一级。第二级能够具有流过第二级的第二电流。第三级能够输出输出电压并能够使第三电流流过第二级。在基本为零的输出电流和最大输出电流之间，电压调节器的整个操作范围中，第一，第二和第三电流彼此成比例。第一级驱动第二级作为低输入阻抗负载。

10. 发明授权

US07126319B2 Low leakage CMOS power mux 失效
标题翻译：低漏电CMOS电源多路复用器
公开(公告)号：US07126319B2
公开(公告)日：2006-10-24
申请号：US11055088
申请日：2005-02-11
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： G05F3/16
CPC分类号： G05F1/575
摘要： A power supply multiplexing circuit including a first supply voltage input. A first pair of cascoded PMOS transistors are in series with the first supply voltage input. A first native NMOS transistor is in series with the first pair of cascoded PMOS transistors. Also, a second supply voltage input and a second pair of cascoded PMOS transistors are in series with the second supply voltage input; and a second native NMOS transistor in series with the second pair of cascoded PMOS transistors. The gates of the first and second native NMOS transistors are driven by two control signals out of phase with each other, and sources of the first and second native NMOS transistors are connected together to output an output voltage.
摘要翻译：一种电源复用电路，包括第一电源电压输入。第一对级联PMOS晶体管与第一电源电压输入串联。第一本机NMOS晶体管与第一对级联PMOS晶体管串联。此外，第二电源电压输入和第二对级联的PMOS晶体管与第二电源电压输入串联; 以及与第二对级联的PMOS晶体管串联的第二本机NMOS晶体管。第一和第二天然NMOS晶体管的栅极由彼此异相的两个控制信号驱动，第一和第二天然NMOS晶体管的源极连接在一起以输出输出电压。

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