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1. 发明授权

US08804793B2 Method and apparatus for fast link recovery 有权
标题翻译：快速链路恢复的方法和装置
公开(公告)号：US08804793B2
公开(公告)日：2014-08-12
申请号：US12857080
申请日：2010-08-16
申请人： Jiangfeng Wu , Jose Tellado , John Dring , Nima Ferdosi
发明人： Jiangfeng Wu , Jose Tellado , John Dring , Nima Ferdosi
IPC分类号： H04B1/38
CPC分类号： H04L25/03343 , H04L1/0014 , H04L1/0025 , H04L1/004 , H04L2025/03802
摘要： Embodiments of methods and apparatus for fast link recover are disclosed. One method includes sensing a link quality failure of a link between a receiver and a transmitter. If a link quality failure is sensed, then the receiver selects new pre-coder settings for the transmitter. The receiver communicates the new pre-coder settings to the transmitter. The transmitter applies the new pre-coder settings. The receiver computes its equalizer settings based on the new pre-coder settings of the transmitter. One apparatus or transceiver includes a means for determining a link quality failure of a link between the transceiver and a link partner transceiver. The transceiver selects new pre-coder settings for the link partner transceiver if a link quality failure is sensed. Additionally, the transceiver communicates the new pre-coder settings to the link partner transceiver, and computes its equalizer settings based on the new pre-coder settings of the link partner transceiver.
摘要翻译：公开了用于快速链路恢复的方法和装置的实施例。一种方法包括感测接收机和发射机之间的链路的链路质量故障。如果感测到链路质量故障，则接收机为发射机选择新的预编码器设置。接收机将新的预编码器设置传送给发射机。发射机应用新的预编码器设置。接收机根据发射机的新的预编码器设置计算其均衡器设置。一种装置或收发器包括用于确定收发器和链路伙伴收发器之间的链路的链路质量故障的装置。如果感测到链路质量故障，收发器将为链路伙伴收发器选择新的预编码器设置。此外，收发器将新的预编码器设置传送到链路伙伴收发器，并且基于链路伙伴收发器的新的预编码器设置来计算其均衡器设置。

2. 发明申请

US20120062311A1 System including adaptive power rails and related method 有权
标题翻译：系统包括自适应电源轨及相关方法
公开(公告)号：US20120062311A1
公开(公告)日：2012-03-15
申请号：US13065720
申请日：2011-03-28
申请人： Chun-Ying Chen , Jiangfeng Wu
发明人： Chun-Ying Chen , Jiangfeng Wu
IPC分类号： G05F3/02
CPC分类号： H03K19/018521 , H03K19/018571
摘要： According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.
摘要翻译：根据一个公开的实施例，描述了一种用于将低压器件与高压模拟电路集成的自适应电压轨电路。该自适应电压轨电路包括具有共模电压的高压模拟电路。还包括第一电压轨，其具有基于并且大于高压模拟电路的共模电压的第一轨电压。还存在具有基于且小于相同共模电压的第二导轨电压的第二电压轨。通过将这些第一和第二电压轨连接到至少一个低电压器件上，自适应电压轨电路能够将低电压器件与同一系统中的高电压模拟电路安全地集成。

3. 发明授权

US06510190B1 Method and apparatus for estimating fading distortion of a signal propagating in a communication channel 有权
标题翻译：用于估计在通信信道中传播的信号的衰落失真的方法和装置
公开(公告)号：US06510190B1
公开(公告)日：2003-01-21
申请号：US09213154
申请日：1998-12-17
申请人： Jiangfeng Wu , Jan Corneliu Olivier , Chengshan Xiao
发明人： Jiangfeng Wu , Jan Corneliu Olivier , Chengshan Xiao
IPC分类号： H04L700
CPC分类号： H04L1/20
摘要： The present invention relates to a method and an apparatus for compensating a signal that has experienced fading distortion in a communication channel. The signal that can be a TDMA (Time Division Multiple Access) signal includes slots that carry data symbols. Non-uniformly spaced pilot symbols are also embedded in the slot structure. The receiver separates the incoming symbols stream in two parts namely a pilot symbols stream and data symbols stream. Since the transmitted pilot symbols are known, an estimate of the channel distortion on the pilot symbols locations can be computed. This estimate is then interpolated to provide an estimate of the fading distortion at the data symbols locations, thus allowing to compensate accurately for the fading distortion in the channel.
摘要翻译：本发明涉及一种补偿在通信信道中经历衰落失真的信号的方法和装置。可以是TDMA（时分多址）信号的信号包括携带数据符号的时隙。非均匀间隔的导频符号也嵌入槽结构中。接收机将输入符号流分成两部分，即导频符号流和数据符号流。由于发送的导频符号是已知的，因此可以计算导频符号位置处的信道失真的估计。然后对该估计进行内插以提供数据符号位置处的衰落失真的估计，从而允许准确地补偿信道中的衰落失真。

4. 发明授权

US08686888B2 Complementary switched capacitor amplifier for pipelined ADCs and other applications 有权
标题翻译：用于流水线ADC和其他应用的互补开关电容放大器
公开(公告)号：US08686888B2
公开(公告)日：2014-04-01
申请号：US13543386
申请日：2012-07-06
申请人： Wei-Te Chou , Jiangfeng Wu , Wenbo Liu
发明人： Wei-Te Chou , Jiangfeng Wu , Wenbo Liu
IPC分类号： H03M1/38
CPC分类号： H03F3/005 , H03F3/265 , H03F3/3001 , H03F3/45179 , H03F2203/45551 , H03M1/164
摘要： The present disclosure is directed to a switched capacitor amplifier that includes a switched capacitor network and a complementary push-pull amplifier. The switched capacitor amplifier of the present disclosure can provide a larger fraction of the charge provided by a power supply and flowing through the amplifier to a capacitive load at the output of the amplifier compared to switched capacitor amplifiers that use single-ended class-A amplifiers. The switched capacitor amplifier of the present disclosure can be used in a converter stage of a pipelined analog-to-digital converter (ADC) to improve the ADC's power efficiency and/or bandwidth. It can be further generalized to be used in other applications other than pipelined ADCs.
摘要翻译：本公开涉及一种包括开关电容器网络和互补推挽放大器的开关电容放大器。与使用单端A类放大器的开关电容放大器相比，本公开的开关电容放大器可以提供由电源提供并且在放大器的输出处流过放大器的电容性负载的较大部分电荷，。本公开的开关电容放大器可用于流水线模数转换器（ADC）的转换器级，以提高ADC的功率效率和/或带宽。可以进一步推广使用流水线ADC以外的其他应用。

5. 发明申请

US20130085703A1 Histogram-Based Linearization of Analog-to-Digital Converters 审中-公开
标题翻译：模数转换器的基于直方图的线性化
公开(公告)号：US20130085703A1
公开(公告)日：2013-04-04
申请号：US13249845
申请日：2011-09-30
申请人： Ray (Ramon) GOMEZ , Bruce J. Currivan , Lin He , Loke Tan , Frank Van der Goes , Cy (Chun-Ying) Chen , Jiangfeng Wu , Thomas Kolze
发明人： Ray (Ramon) GOMEZ , Bruce J. Currivan , Lin He , Loke Tan , Frank Van der Goes , Cy (Chun-Ying) Chen , Jiangfeng Wu , Thomas Kolze
IPC分类号： G06F17/17 , G06F19/00
CPC分类号： G06F17/17 , H03M1/1042 , H03M1/12
摘要： Embodiments provide histogram-based methods and system to estimate the transfer function of an ADC, and subsequently to linearize a non-linear ADC transfer function. Embodiments include blind algorithms that require no a priori knowledge of the input signal distribution. Embodiments can be implemented using cumulative (i.e., cumulative distribution function (CDF)) or non-cumulative (i.e., probability density function (PDF)) histograms. According to embodiments, a non-linear transfer function can be estimated by linearly approximating successive local intervals of the transfer function. Linearly approximated successive local intervals of the transfer function can then be used to fully characterize and closely estimate the transfer function.
摘要翻译：实施例提供基于直方图的方法和系统来估计ADC的传递函数，并且随后对非线性ADC传递函数进行线性化。实施例包括不需要输入信号分布的先验知识的盲算法。实施例可以使用累积（即，累积分布函数（CDF））或非累积（即，概率密度函数（PDF））直方图来实现。根据实施例，可以通过线性近似传递函数的连续局部间隔来估计非线性传递函数。传递函数的线性逼近的连续局部间隔可用于完全表征和密切估计传递函数。

6. 发明授权

US07890080B2 Multi-protocol radio frequency identification transceiver 有权
标题翻译：多协议射频识别收发器
公开(公告)号：US07890080B2
公开(公告)日：2011-02-15
申请号：US12711934
申请日：2010-02-24
申请人： Jiangfeng Wu , Donald Edward Major
发明人： Jiangfeng Wu , Donald Edward Major
IPC分类号： H04B1/16
CPC分类号： G06K7/0008
摘要： A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.
摘要翻译：用于RFID读取器的收发器和用于RFID应答器（标签）的收发器允许两个设备之间的通信。 RFID阅读器使用模拟前端和数字后端。在收发器的接收器部分中，RFID读取器的前端使用一对下变频混频器将接收的信号解调为同相（I）和正交（Q）分量和模数转换器（ADC））数字化信号。后端的数字信号处理器（DSP）处理数字信号，并使用匹配滤波器进行数据检测。 RFID标签从读取器接收电感耦合信号，并且标签的接收器部分使用采用模拟比较器和采样和保持电路来检测接收信号的脉冲/电平检测器。数字解码器/控制器用于对输入数据进行解码并建立脉冲/电平检测器的采样时钟。自动增益控制（AGC）电路根据接收到的信号强度调整接收机增益，并控制磁耦合电路的调谐。

7. 发明申请

US20060186995A1 Multi-protocol radio frequency identification reader tranceiver 有权
公开(公告)号：US20060186995A1
公开(公告)日：2006-08-24
申请号：US11154231
申请日：2005-06-16
申请人： Jiangfeng Wu , Donald Major
发明人： Jiangfeng Wu , Donald Major
IPC分类号： H04Q5/22
CPC分类号： G06K7/0008 , H04B1/30 , H04B1/408
摘要： A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

8. 发明授权

US06614273B2 Ultra-fast voltage drive 有权
公开(公告)号：US06614273B2
公开(公告)日：2003-09-02
申请号：US09772776
申请日：2001-01-30
申请人： Patrick Teterud , Jiangfeng Wu , Thomas Van Eaton
发明人： Patrick Teterud , Jiangfeng Wu , Thomas Van Eaton
IPC分类号： G11B503
CPC分类号： H03K17/666 , H03K17/04126
摘要： An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N1). A pair of bipolar output transistors (Q3, Q4) are selectively driven via a FET drive circuit (42), and by a control circuit (44) to achieve a rail-to-rail output voltage (Vcc−Vee) that is very fast. The drive FETs comprise three serially connected FETs (M5, M6, M7) whereby the middle FET (M6) is the control FET effecting the control of the output transistors (Q3, Q4). The other two FETs (M5, M7) are always in the on state and complete either the pull-up or pull-down of the voltage at the output node (N1), depending on the state of the middle FET (M6). The control FETs (44) provide two output control signals (46, 48) to the output transistors (Q3, Q4), with the control line (48) controlling the state of the middle switching FET (M6).

9. 发明授权

US08427228B2 System including adaptive power rails and related method 有权
标题翻译：系统包括自适应电源轨及相关方法
公开(公告)号：US08427228B2
公开(公告)日：2013-04-23
申请号：US13065720
申请日：2011-03-28
申请人： Chun-Ying Chen , Jiangfeng Wu
发明人： Chun-Ying Chen , Jiangfeng Wu
IPC分类号： G05F1/10
CPC分类号： H03K19/018521 , H03K19/018571
摘要： According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.
摘要翻译：根据一个公开的实施例，描述了一种用于将低压器件与高压模拟电路集成的自适应电压轨电路。该自适应电压轨电路包括具有共模电压的高压模拟电路。还包括第一电压轨，其具有基于并且大于高压模拟电路的共模电压的第一轨电压。还存在具有基于且小于相同共模电压的第二导轨电压的第二电压轨。通过将这些第一和第二电压轨连接到至少一个低电压器件上，自适应电压轨电路能够将低电压器件与同一系统中的高电压模拟电路安全地集成。

10. 发明申请

US20100148929A1 Multi-protocol radio frequency identification transceiver 有权
标题翻译：多协议射频识别收发器
公开(公告)号：US20100148929A1
公开(公告)日：2010-06-17
申请号：US12711934
申请日：2010-02-24
申请人： Jiangfeng Wu , Donald Edward Major
发明人： Jiangfeng Wu , Donald Edward Major
IPC分类号： H04Q5/22
CPC分类号： G06K7/0008
摘要： A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.
摘要翻译：用于RFID读取器的收发器和用于RFID应答器（标签）的收发器允许两个设备之间的通信。 RFID阅读器使用模拟前端和数字后端。在收发器的接收器部分中，RFID读取器的前端使用一对下变频混频器将接收的信号解调为同相（I）和正交（Q）分量和模数转换器（ADC））数字化信号。后端的数字信号处理器（DSP）处理数字信号，并使用匹配滤波器进行数据检测。 RFID标签从读取器接收电感耦合信号，并且标签的接收器部分使用采用模拟比较器和采样和保持电路来检测接收信号的脉冲/电平检测器。数字解码器/控制器用于对输入数据进行解码并建立脉冲/电平检测器的采样时钟。自动增益控制（AGC）电路根据接收到的信号强度调整接收机增益，并控制磁耦合电路的调谐。

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