专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5675549A Burst EDO memory device address counter 失效
标题翻译：突发EDO存储设备地址计数器
公开(公告)号：US5675549A
公开(公告)日：1997-10-07
申请号：US457651
申请日：1995-06-01
申请人： Adrian Ong , Paul S. Zagar , Brett L. Wiliams , Troy A. Manning
发明人： Adrian Ong , Paul S. Zagar , Brett L. Wiliams , Troy A. Manning
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/109 , G11C7/1096 , G06F2212/2022
摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
摘要翻译：由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件。将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

2. 发明授权

US5802010A Burst EDO memory device 失效
公开(公告)号：US5802010A
公开(公告)日：1998-09-01
申请号：US661478
申请日：1996-06-10
申请人： Paul S. Zagar , Brett L. Williams , Troy A. Manning
发明人： Paul S. Zagar , Brett L. Williams , Troy A. Manning
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

3. 发明授权

US5668773A Synchronous burst extended data out DRAM 失效
标题翻译：同步突发扩展数据输出DRAM
公开(公告)号：US5668773A
公开(公告)日：1997-09-16
申请号：US552199
申请日：1995-11-02
申请人： Paul S. Zagar , Troy A. Manning , Todd Merritt
发明人： Paul S. Zagar , Troy A. Manning , Todd Merritt
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additioned memory addresses. A clock signed is provided to synchronize the burst operations. The clock signed is independent of an address latch signal used to latch an external address.
摘要翻译：描述了可以以高数据速度操作的集成电路存储器件。存储器设备可以在突发存取操作中存储或从存储器检索数据。突发操作从外部地址线锁存存储器地址，并在内部生成加法存储器地址。提供了一个签名的时钟以使突发操作同步。所签的时钟独立于用于锁存外部地址的地址锁存信号。

4. 发明授权

US5526320A Burst EDO memory device 失效
标题翻译： Burst EDO存储设备
公开(公告)号：US5526320A
公开(公告)日：1996-06-11
申请号：US370761
申请日：1994-12-23
申请人： Paul S. Zagar , Brett L. Williams , Troy A. Manning
发明人： Paul S. Zagar , Brett L. Williams , Troy A. Manning
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
摘要翻译：集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。地址选通信号用于锁存第一个地址。在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。

5. 发明授权

US5812488A Synchronous burst extended data out dram 失效
标题翻译：同步突发扩展数据输出
公开(公告)号：US5812488A
公开(公告)日：1998-09-22
申请号：US811696
申请日：1997-03-05
申请人： Paul S. Zagar , Troy A. Manning , Todd Merritt
发明人： Paul S. Zagar , Troy A. Manning , Todd Merritt
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. A clock signal is provided to synchronize the burst operations. The clock signal is independent of an address latch signal used to latch an external address.
摘要翻译：描述了可以在高数据速度下操作的集成电路存储器件。存储器设备可以在突发存取操作中存储或从存储器检索数据。突发操作从外部地址线锁存存储器地址，并在内部生成额外的存储器地址。提供时钟信号以同步突发操作。时钟信号与用于锁存外部地址的地址锁存信号无关。

6. 发明授权

US5850368A Burst EDO memory address counter 失效
标题翻译：突发EDO内存地址计数器
公开(公告)号：US5850368A
公开(公告)日：1998-12-15
申请号：US922194
申请日：1997-09-02
申请人： Adrian E. Ong , Paul S. Zagar , Brett L. Williams , Troy A. Manning
发明人： Adrian E. Ong , Paul S. Zagar , Brett L. Williams , Troy A. Manning
IPC分类号： G11C8/04 , G11C8/00
CPC分类号： G11C8/04
摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
摘要翻译：由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件。将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

7. 发明授权

US5293342A Wordline driver circuit having an automatic precharge circuit 失效
标题翻译：字线驱动电路具有自动预充电电路
公开(公告)号：US5293342A
公开(公告)日：1994-03-08
申请号：US993929
申请日：1992-12-17
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.
摘要翻译：本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。预充电装置由行解码器的解码部分的主要预解码信号自动选通。功率节省，因为串行节点被动地通过预充电器件拉到电源电位。本发明提高了速度并提供了无错误的字线选择。

8. 发明授权

US5999480A Dynamic random-access memory having a hierarchical data path 有权
标题翻译：具有分层数据路径的动态随机存取存储器
公开(公告)号：US5999480A
公开(公告)日：1999-12-07
申请号：US167259
申请日：1998-10-06
申请人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.
摘要翻译：一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，其集合和/或单独证明在所公开的诸如密度，功耗，速度和冗余度之类的考虑方面是有益和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本相同的1M位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了分层数据路径，其中多个复用器分布在每个SAB中，这些多路复用器用于选择性地将感测放大器输出信号耦合到与每个SAB相关联的本地数据I / O线。在一个实施例中，数据路径多路复用器物理地布置在分布在每个SAB中的相邻的本地行地址解码器限定的间隙内。

9. 再颁专利

USRE35750E Wordline driver circuit having an automatic precharge circuit 失效
标题翻译：字线驱动电路具有自动预充电电路
公开(公告)号：USRE35750E
公开(公告)日：1998-03-24
申请号：US611618
申请日：1996-03-08
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.
摘要翻译：本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。预充电装置由行解码器的解码部分的主要预解码信号自动选通。功率节省，因为串行节点被动地通过预充电器件拉到电源电位。本发明提高了速度并提供了无错误的字线选择。

10. 发明授权

US5311481A Wordline driver circuit having a directly gated pull-down device 失效
标题翻译：字线驱动电路具有直接门控下拉装置
公开(公告)号：US5311481A
公开(公告)日：1994-05-10
申请号：US993934
申请日：1992-12-17
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
摘要翻译：本发明是用于快速驱动未选择的字线以纠正电位的电路和方法。本发明通过由解码电路产生的初级选择预解码信号直接选通的驱动装置将未选择的字线驱动到低电位。驱动装置电插入字线和参考节点之间。本发明提供低功率操作，并且为电源电压低于5伏的电路提供可靠的字线选择。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式