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1. 发明授权

US06742112B1 Lookahead register value tracking 有权
标题翻译：前瞻寄存器值跟踪
公开(公告)号：US06742112B1
公开(公告)日：2004-05-25
申请号：US09473976
申请日：1999-12-29
申请人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
发明人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
IPC分类号： G06F934
CPC分类号： G06F9/30134 , G06F9/30167 , G06F9/383 , G06F9/3832 , G06F9/3842
摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.
摘要翻译：跟踪寄存器值的装置和方法。微处理器可以包括第一寄存器，控制电路和加法器。第一个寄存器可以存储跟踪的寄存器值。控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。

2. 发明授权

US07017026B2 Generating lookahead tracked register value based on arithmetic operation indication 失效
标题翻译：基于算术运算指示生成前瞻追踪寄存器值
公开(公告)号：US07017026B2
公开(公告)日：2006-03-21
申请号：US10848602
申请日：2004-05-18
申请人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
发明人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
IPC分类号： G06F9/34
CPC分类号： G06F9/30134 , G06F9/30167 , G06F9/383 , G06F9/3832 , G06F9/3842
摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.
摘要翻译：跟踪寄存器值的装置和方法。微处理器可以包括第一寄存器，控制电路和加法器。第一个寄存器可以存储跟踪的寄存器值。控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。

3. 发明授权

US06880063B2 Memory cache bank prediction 有权
标题翻译：内存缓存库预测
公开(公告)号：US06880063B2
公开(公告)日：2005-04-12
申请号：US10755017
申请日：2004-01-09
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。存储器缓存库预测单元具有接收指令的输入端口。存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

4. 发明授权

US07644236B2 Memory cache bank prediction 失效
标题翻译：内存缓存库预测
公开(公告)号：US07644236B2
公开(公告)日：2010-01-05
申请号：US11045528
申请日：2005-01-28
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F12/00
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。存储器缓存库预测单元具有接收指令的输入端口。存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

5. 发明授权

US08285976B2 Method and apparatus for predicting branches using a meta predictor 有权
标题翻译：使用元预测器预测分支的方法和装置
公开(公告)号：US08285976B2
公开(公告)日：2012-10-09
申请号：US09749405
申请日：2000-12-28
申请人： Stephan J. Jourdan , Adi Yoaz , Mattan Erez , Ronny Ronen
发明人： Stephan J. Jourdan , Adi Yoaz , Mattan Erez , Ronny Ronen
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3848
摘要： A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction apparatus includes a meta predictor that receives an index value and a branch prediction to generate a misprediction value in accordance with the base misprediction history register. The branch prediction apparatus also includes a logic gate that receives the branch prediction and the misprediction value to generate a final prediction. The final prediction may be used to predict whether a branch is taken or not taken.
摘要翻译：公开了一种分支预测装置，其减少处理器中的分支错误预测。分支预测装置包括基本错误预测历史寄存器。分支预测装置包括元预测器，其接收索引值和分支预测，以根据基本错误预测历史寄存器生成错误预测值。分支预测装置还包括接收分支预测和误预测值以产生最终预测的逻辑门。最终预测可用于预测是否采取分支。

6. 发明授权

US06516405B1 Method and system for safe data dependency collapsing based on control-flow speculation 失效
标题翻译：基于控制流猜测的安全数据依赖性崩溃的方法和系统
公开(公告)号：US06516405B1
公开(公告)日：2003-02-04
申请号：US09475646
申请日：1999-12-30
申请人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
发明人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
IPC分类号： G06F945
CPC分类号： G06F9/30094 , G06F9/383 , G06F9/3832 , G06F9/384 , G06F9/3842 , G06F9/3863
摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.
摘要翻译：本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

7. 发明授权

US06505293B1 Register renaming to optimize identical register values 失效
标题翻译：注册重命名以优化相同的寄存器值
公开(公告)号：US06505293B1
公开(公告)日：2003-01-07
申请号：US09348973
申请日：1999-07-07
申请人： Stephan J. Jourdan , Ronny Ronen , Adi Yoaz
发明人： Stephan J. Jourdan , Ronny Ronen , Adi Yoaz
IPC分类号： G06F938
CPC分类号： G06F9/30032 , G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A processor architecture for providing many-to-one mappings between logical registers and physical registers, so that more than one logical register may map to the same physical register. Each physical register has an associated counter to indicate whether the physical register is free. A counter is incremented each time a mapping is made to its associated physical register, and is decremented when that mapping is no longer needed. If a logical register named in a decoded instruction is predicted to have the same value as a value stored in a physical register, then the logical register is mapped to the physical register.
摘要翻译：一种用于在逻辑寄存器和物理寄存器之间提供多对一映射的处理器架构，使得多于一个逻辑寄存器可映射到相同的物理寄存器。每个物理寄存器都有一个关联的计数器，用于指示物理寄存器是否空闲。每当对其相关联的物理寄存器进行映射时，计数器递增，并且当不再需要该映射时递减计数器。如果预测在解码指令中命名的逻辑寄存器具有与存储在物理寄存器中的值相同的值，则逻辑寄存器被映射到物理寄存器。

8. 发明授权

US07284116B2 Method and system for safe data dependency collapsing based on control-flow speculation 有权
标题翻译：基于控制流猜测的安全数据依赖性崩溃的方法和系统
公开(公告)号：US07284116B2
公开(公告)日：2007-10-16
申请号：US10307557
申请日：2002-12-02
申请人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
发明人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
IPC分类号： G06F9/34
CPC分类号： G06F9/30094 , G06F9/383 , G06F9/3832 , G06F9/384 , G06F9/3842 , G06F9/3863
摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.
摘要翻译：本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

9. 发明授权

US06694421B2 Cache memory bank access prediction 有权
标题翻译：缓存存储器存取预测
公开(公告)号：US06694421B2
公开(公告)日：2004-02-17
申请号：US09474381
申请日：1999-12-29
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F1208
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个高速缓存存储体的处理器中的高速缓存存储体预测单元。高速缓存库预测单元具有接收指令的输入端口。高速缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个高速缓存组中的哪一个与该指令相关联。

10. 发明授权

US06772317B2 Method and apparatus for optimizing load memory accesses 失效
标题翻译：用于优化加载存储器访问的方法和装置
公开(公告)号：US06772317B2
公开(公告)日：2004-08-03
申请号：US09861050
申请日：2001-05-17
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
IPC分类号： G06F9312
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3832 , G06F9/384
摘要： A computer architecture to process load instructions by allowing multiple mappings between logical registers and the same physical register is disclosed. The computer architecture includes a processor having a physical registers. The processor also includes a decoder to decode a load instruction that names a destination logical register. The processor also includes a register allocation table to map the destination logical register to a physical register within the plurality of physical registers. If the load instruction is predicted to collide with a prior load instruction that names a destination logical register, then the register allocation table maps the destination logical register to the physical register allocated to the first load instruction.
摘要翻译：公开了通过允许逻辑寄存器和相同物理寄存器之间的多个映射来处理加载指令的计算机体系结构。计算机体系结构包括具有物理寄存器的处理器。处理器还包括解码器，用于解码命名目的地逻辑寄存器的加载指令。处理器还包括寄存器分配表，以将目的地逻辑寄存器映射到多个物理寄存器内的物理寄存器。如果预期加载指令与命名目的地逻辑寄存器的先前加载指令相冲突，则寄存器分配表将目的地逻辑寄存器映射到分配给第一加载指令的物理寄存器。

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