专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06742112B1 Lookahead register value tracking 有权
标题翻译：前瞻寄存器值跟踪
公开(公告)号：US06742112B1
公开(公告)日：2004-05-25
申请号：US09473976
申请日：1999-12-29
申请人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
发明人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
IPC分类号： G06F934
CPC分类号： G06F9/30134 , G06F9/30167 , G06F9/383 , G06F9/3832 , G06F9/3842
摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.
摘要翻译：跟踪寄存器值的装置和方法。微处理器可以包括第一寄存器，控制电路和加法器。第一个寄存器可以存储跟踪的寄存器值。控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。

2. 发明授权

US07017026B2 Generating lookahead tracked register value based on arithmetic operation indication 失效
标题翻译：基于算术运算指示生成前瞻追踪寄存器值
公开(公告)号：US07017026B2
公开(公告)日：2006-03-21
申请号：US10848602
申请日：2004-05-18
申请人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
发明人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
IPC分类号： G06F9/34
CPC分类号： G06F9/30134 , G06F9/30167 , G06F9/383 , G06F9/3832 , G06F9/3842
摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.
摘要翻译：跟踪寄存器值的装置和方法。微处理器可以包括第一寄存器，控制电路和加法器。第一个寄存器可以存储跟踪的寄存器值。控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。

3. 发明授权

US06678808B2 Memory record update filtering 有权
标题翻译：内存记录更新过滤
公开(公告)号：US06678808B2
公开(公告)日：2004-01-13
申请号：US10384531
申请日：2003-03-11
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F1200
CPC分类号： G06F9/3806 , G06F12/126
摘要： Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.
摘要翻译：用于过滤内存记录更新的设备和方法。微处理器可以包括存储器记录更新过滤器。存储器记录更新过滤器可以包括由多个数据条目填充的表存储器。每个数据条目可以包括用于存储数据标签的数据标签字段，用于存储数据值的数据字段和用于存储过滤器值的过滤器字段。第一比较器可以与表存储器的数据标签字段进行通信，以及数据访问信息输入以执行数据标签比较。第二比较器可以与表存储器的滤波器字段进行通信，并且与数据值输入通信。控制电路可以与表存储器，第一比较器和第二比较器通信。

4. 发明授权

US06772317B2 Method and apparatus for optimizing load memory accesses 失效
标题翻译：用于优化加载存储器访问的方法和装置
公开(公告)号：US06772317B2
公开(公告)日：2004-08-03
申请号：US09861050
申请日：2001-05-17
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
IPC分类号： G06F9312
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3832 , G06F9/384
摘要： A computer architecture to process load instructions by allowing multiple mappings between logical registers and the same physical register is disclosed. The computer architecture includes a processor having a physical registers. The processor also includes a decoder to decode a load instruction that names a destination logical register. The processor also includes a register allocation table to map the destination logical register to a physical register within the plurality of physical registers. If the load instruction is predicted to collide with a prior load instruction that names a destination logical register, then the register allocation table maps the destination logical register to the physical register allocated to the first load instruction.
摘要翻译：公开了通过允许逻辑寄存器和相同物理寄存器之间的多个映射来处理加载指令的计算机体系结构。计算机体系结构包括具有物理寄存器的处理器。处理器还包括解码器，用于解码命名目的地逻辑寄存器的加载指令。处理器还包括寄存器分配表，以将目的地逻辑寄存器映射到多个物理寄存器内的物理寄存器。如果预期加载指令与命名目的地逻辑寄存器的先前加载指令相冲突，则寄存器分配表将目的地逻辑寄存器映射到分配给第一加载指令的物理寄存器。

5. 发明授权

US06625723B1 Unified renaming scheme for load and store instructions 有权
标题翻译：用于加载和存储指令的统一重命名方案
公开(公告)号：US06625723B1
公开(公告)日：2003-09-23
申请号：US09348403
申请日：1999-07-07
申请人： Stephen J. Jourday , Adi Yoaz , Ronny Ronen , Michael Bekerman
发明人： Stephen J. Jourday , Adi Yoaz , Ronny Ronen , Michael Bekerman
IPC分类号： G06F938
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3834 , G06F9/3838 , G06F9/384
摘要： A computer architecture for collapsing dependency graphs for colliding store and load instructions. Many-to-one mappings are provided between logical registers and physical registers, so that more than one logical register may map to the same physical register. For a load instruction that is predicted to collide with an earlier in-flight store instruction, the destination logical register of the load instruction is mapped to the same physical register to which the source logical register of the earlier in-flight store instruction is mapped. A many-to-one mapping may be realized by associating a counter with each physical register, so that the value of a counter indicates whether its associated physical counter is free.
摘要翻译：用于折叠依赖关系图以用于存储和加载指令的计算机体系结构。在逻辑寄存器和物理寄存器之间提供多对一映射，以便多个逻辑寄存器可映射到同一个物理寄存器。对于预计与较早的飞行中存储指令相冲突的加载指令，加载指令的目的地逻辑寄存器被映射到映射了较早的飞行中存储指令的源逻辑寄存器的同一物理寄存器。可以通过将计数器与每个物理寄存器相关联来实现多对一映射，使得计数器的值指示其相关联的物理计数器是否是空闲的。

6. 发明授权

US07428627B2 Method and apparatus for predicting values in a processor having a plurality of prediction modes 失效
标题翻译：用于预测具有多种预测模式的处理器中的值的方法和装置
公开(公告)号：US07428627B2
公开(公告)日：2008-09-23
申请号：US09750150
申请日：2000-12-29
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F9/3844
摘要： A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP table includes a plurality of PIP information fields and the next value table includes a plurality of fields. The multi-mode predictor also includes a plurality of prediction modes. The processor includes a set of instructions that index the PIP table to provide a valid signal. The processor also includes a set of predicted values for the set of instructions. The set of predicted values is stored in the PIP table and the next value table. According to the valid signal a hit/miss condition in the next value table, a predicted value is selected from the PIP table or the next value table.
摘要翻译：公开了一种具有多种预测模式的处理器的多模式预测器。预测模式用于预测非二进制值。预测器是包括每IP（“PIP”）表和下一个值表的多模式预测器。 PIP表包括多个PIP信息字段，下一个值表包括多个字段。多模式预测器还包括多种预测模式。处理器包括一组索引PIP表以提供有效信号的指令。处理器还包括用于该组指令的一组预测值。预测值的集合存储在PIP表和下一个值表中。根据有效信号在下一个值表中的命中/未命中条件，从PIP表或下一个值表中选择预测值。

7. 发明授权

US06553469B2 Memory record update filtering 有权
公开(公告)号：US06553469B2
公开(公告)日：2003-04-22
申请号：US10153920
申请日：2002-05-24
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F1200
CPC分类号： G06F9/3806 , G06F12/126
摘要： Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.

8. 发明授权

US06438673B1 Correlated address prediction 有权
标题翻译：相关地址预测
公开(公告)号：US06438673B1
公开(公告)日：2002-08-20
申请号：US09475063
申请日：1999-12-30
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862 , G06F2212/6024
摘要： A microprocessor having a correlated address predictor, and methods of performing correlated address prediction. A first table memory can be populated by a plurality of buffer entries. Each buffer entry can include a first buffer field to store a first tag based on an instruction pointer and a second buffer field to store an address history. A second table memory can be populated by a plurality of link entries. Each link entry can include a first link field to store a link tag based on an address history and a second link field to store a predicted address. A first comparator can be in communication with the first table memory and an instruction pointer input. A second comparator can be in communication with the first table memory and the second table memory. An output in communication with the second table memory.
摘要翻译：具有相关地址预测器的微处理器，以及执行相关地址预测的方法。第一表存储器可以由多个缓冲器入口填充。每个缓冲器条目可以包括基于指令指针存储第一标签的第一缓冲区域和用于存储地址历史的第二缓冲区域。第二表存储器可以由多个链接条目填充。每个链接条目可以包括基于地址历史存储链接标签的第一链接字段和用于存储预测地址的第二链接字段。第一比较器可以与第一表存储器和指令指针输入通信。第二比较器可以与第一表存储器和第二表存储器通信。与第二表存储器通信的输出。

9. 发明授权

US07539850B2 Enhanced virtual renaming scheme and deadlock prevention therefor 失效
标题翻译：增强的虚拟重命名方案和防止死锁
公开(公告)号：US07539850B2
公开(公告)日：2009-05-26
申请号：US10351444
申请日：2003-01-27
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F9/34
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
摘要翻译：在处理器内的增强型虚拟重命名方案中，可以将多个逻辑寄存器映射到单个物理寄存器。值缓存确定根据程序指令生成的新值是否与先前执行的指令相关联的值匹配。如果是，则与新执行的指令相关联的逻辑寄存器共享物理寄存器。此外，死锁预防措施可以以在处理器核心中产生来自旧指令的值产生时从较小执行指令“窃取”物理寄存器的方式集成到寄存器分配单元中。

10. 发明授权

US07155599B2 Method and apparatus for a register renaming structure 有权
标题翻译：一种寄存器重命名结构的方法和装置
公开(公告)号：US07155599B2
公开(公告)日：2006-12-26
申请号：US09750095
申请日：2000-12-29
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
IPC分类号： G06F9/40
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3857
摘要： A processor having a register renaming structure and method is disclosed to recover a free list. The processor includes a physical register file including physical registers. The processor also includes a decoder to decode an instruction to indicate a destination logical register. The processor also includes a register allocation table to map the destination logical register to an allocated physical register. The processor also includes an active list that includes an old field and a new field. The old field includes at least one evicted physical register from the register alias table. The new field includes the allocated physical register. The processor also includes the free list of unallocated physical registers reclaimed from the active list.
摘要翻译：公开了具有寄存器重命名结构和方法的处理器来恢复空闲列表。该处理器包括一个包括物理寄存器的物理寄存器文件。处理器还包括解码器，用于解码指示目的地逻辑寄存器的指令。处理器还包括寄存器分配表，以将目的地逻辑寄存器映射到所分配的物理寄存器。该处理器还包括一个包含旧字段和新字段的活动列表。旧字段至少包含一个从寄存器别名表中删除的物理寄存器。新的领域包括分配的物理寄存器。处理器还包括从活动列表中回收的未分配物理寄存器的空闲列表。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式