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1. 发明授权

US11881454B2 Stacked IC structure with orthogonal interconnect layers 有权
公开(公告)号：US11881454B2
公开(公告)日：2024-01-23
申请号：US17201732
申请日：2021-03-15
申请人： ADEIA SEMICONDUCTOR INC.
发明人： Ilyas Mohammed , Steven L. Teig , Javier A. Delacruz
IPC分类号： H01L23/528 , H01L23/00 , H01L23/50 , H01L21/822 , H01L27/06 , H01L23/522 , H01L25/065
CPC分类号： H01L23/5286 , H01L21/8221 , H01L23/50 , H01L23/5225 , H01L24/26 , H01L25/0657 , H01L27/0688 , H01L24/08 , H01L24/16 , H01L2224/08147 , H01L2224/16145 , H01L2224/80895 , H01L2224/80896 , H01L2924/15311
摘要： Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

2. 发明授权

US11790219B2 Three dimensional circuit implementing machine trained network 有权
公开(公告)号：US11790219B2
公开(公告)日：2023-10-17
申请号：US17500374
申请日：2021-10-13
申请人： ADEIA SEMICONDUCTOR INC.
发明人： Steven L. Teig , Kenneth Duong
IPC分类号： G06N3/065 , G06N3/08 , G06N3/04 , H01L25/065 , G06F11/20 , G06N3/084 , G06F11/14 , G06N3/048 , G06N3/063 , G06N3/082 , H01L23/31 , H01L23/00 , H01L25/075 , H01L25/04 , H01L25/11 , H01L25/07 , H03K19/21
CPC分类号： G06N3/065 , G06F11/1423 , G06F11/2007 , G06F11/2028 , G06F11/2041 , G06F11/2051 , G06N3/04 , G06N3/048 , G06N3/063 , G06N3/08 , G06N3/082 , G06N3/084 , H01L23/3128 , H01L25/0657 , G06F2201/85 , H01L24/16 , H01L24/17 , H01L25/043 , H01L25/074 , H01L25/0756 , H01L25/117 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2225/06503 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06565 , H01L2225/06582 , H01L2225/06586 , H01L2924/16235 , H03K19/21
摘要： Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

3. 发明申请

US20230137580A1 3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK 有权
公开(公告)号：US20230137580A1
公开(公告)日：2023-05-04
申请号：US18146709
申请日：2022-12-27
申请人： Adeia Semiconductor Inc.
发明人： Javier A. DeLaCruz , Steven L. Teig , Ilyas Mohammed , Eric M. Nequist
IPC分类号： H01L21/822 , H01L23/00 , H01L23/528 , H01L25/065 , H01L27/06
摘要： Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

4. 发明授权

US11557516B2 3D chip with shared clock distribution network 有权
公开(公告)号：US11557516B2
公开(公告)日：2023-01-17
申请号：US16953113
申请日：2020-11-19
申请人： ADEIA SEMICONDUCTOR INC.
发明人： Javier DeLaCruz , Steven L. Teig , Ilyas Mohammed , Eric M. Nequist
IPC分类号： H01L23/02 , H01L21/822 , H01L23/00 , H01L23/528 , H01L25/065 , H01L27/06 , H01L21/768 , H01L23/50
摘要： Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

5. 发明授权

US11823906B2 Direct-bonded native interconnects and active base die 有权
公开(公告)号：US11823906B2
公开(公告)日：2023-11-21
申请号：US17675396
申请日：2022-02-18
申请人： Adeia Semiconductor Inc.
发明人： Javier A. DeLaCruz , Steven L. Teig , Shaowu Huang , William C. Plants , David Edward Fisch
IPC分类号： H01L21/20 , H01L25/065 , H01L23/00 , H01L21/48 , H01L21/74 , H01L21/82 , H01L23/538 , H01L25/18
CPC分类号： H01L21/2007 , H01L21/4875 , H01L21/743 , H01L21/82 , H01L24/02 , H01L25/0652 , H01L23/538 , H01L25/18 , H01L2924/15311
摘要： Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

6. 发明公开

US20240266325A1 3D CHIP SHARING DATA BUS 审中-公开
公开(公告)号：US20240266325A1
公开(公告)日：2024-08-08
申请号：US18379925
申请日：2023-10-13
申请人： Adeia Semiconductor Inc.
发明人： Javier A. DeLaCruz , Steven L. Teig , Ilyas Mohammed
IPC分类号： H01L25/065 , H01L21/822 , H01L23/00 , H01L23/498 , H01L23/50 , H01L23/522 , H01L23/528 , H01L23/60 , H01L25/00 , H01L27/06
CPC分类号： H01L25/0657 , H01L21/8221 , H01L23/49827 , H01L23/5225 , H01L23/528 , H01L23/5286 , H01L23/60 , H01L24/32 , H01L25/50 , H01L27/0688 , H01L23/50 , H01L24/06 , H01L24/08 , H01L24/80 , H01L2224/05571 , H01L2224/08147 , H01L2224/09181 , H01L2224/80895 , H01L2224/80896
摘要： Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

7. 发明授权

US11916076B2 Device disaggregation for improved performance 有权
公开(公告)号：US11916076B2
公开(公告)日：2024-02-27
申请号：US16915140
申请日：2020-06-29
申请人： Adeia Semiconductor Inc.
发明人： Javier A. Delacruz , Don Draper , Jung Ko , Steven L. Teig
IPC分类号： H01L25/065 , H01L25/00 , H01L27/118
CPC分类号： H01L27/11807 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2027/11838 , H01L2027/11875 , H01L2027/11879 , H01L2027/11881
摘要： The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

8. 发明公开

US20240152743A1 THREE DIMENSIONAL CIRCUIT IMPLEMENTING MACHINE TRAINED NETWORK 审中-公开
公开(公告)号：US20240152743A1
公开(公告)日：2024-05-09
申请号：US18469910
申请日：2023-09-19
申请人： Adeia Semiconductor Inc.
发明人： Steven L. Teig , Kenneth Duong
IPC分类号： G06N3/065 , G06F11/14 , G06F11/20 , G06N3/04 , G06N3/048 , G06N3/063 , G06N3/08 , G06N3/082 , G06N3/084 , H01L23/31 , H01L25/065
CPC分类号： G06N3/065 , G06F11/1423 , G06F11/2007 , G06F11/2028 , G06F11/2041 , G06F11/2051 , G06N3/04 , G06N3/048 , G06N3/063 , G06N3/08 , G06N3/082 , G06N3/084 , H01L23/3128 , H01L25/0657 , H01L24/17 , H01L2224/16227 , H01L2224/17181 , H01L2924/16235
摘要： Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

9. 发明授权

US12142528B2 3D chip with shared clock distribution network 有权
公开(公告)号：US12142528B2
公开(公告)日：2024-11-12
申请号：US18146709
申请日：2022-12-27
申请人： Adeia Semiconductor Inc.
发明人： Javier A. DeLaCruz , Steven L. Teig , Ilyas Mohammed , Eric M. Nequist
IPC分类号： H01L21/822 , H01L23/00 , H01L23/528 , H01L25/065 , H01L27/06 , H01L21/768 , H01L23/50
CPC分类号： H01L21/8221 , H01L23/5286 , H01L24/10 , H01L24/26 , H01L24/49 , H01L25/0657 , H01L27/0688 , H01L21/76898 , H01L23/50 , H01L2224/16225 , H01L2924/15311
摘要： Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

10. 发明公开

US20240265305A1 Direct-Bonded Native Interconnects And Active Base Die 审中-公开
公开(公告)号：US20240265305A1
公开(公告)日：2024-08-08
申请号：US18379907
申请日：2023-10-13
申请人： Adeia Semiconductor Inc.
发明人： Javier A. DeLaCruz , Steven L. Teig , Shaowu Huang , William C. Plants , David Edward Fisch
IPC分类号： G06N20/00 , G06V10/764 , G06V10/774
CPC分类号： G06N20/00 , G06V10/764 , G06V10/774
摘要： Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

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