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1. 发明授权

US07437695B1 Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices 有权
标题翻译：可编程逻辑器件中的存储器和运行时高效分层时序分析方法
公开(公告)号：US07437695B1
公开(公告)日：2008-10-14
申请号：US11100290
申请日：2005-04-05
申请人： Abhishek Ranjan , David A. Knol , Salil R. Raje
发明人： Abhishek Ranjan , David A. Knol , Salil R. Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5031 , G06F17/5054
摘要： A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical portion. The method also can include creating a software representation of the physical portion of the IC. The software representation can specify the local timing constraint and a shell netlist for the physical portion. The method further can include performing a timing analysis upon, at least part of, the circuit design using the software representation.
摘要翻译：对集成电路（IC）的电路设计执行定时分析的方法可以包括选择包括逻辑层级的至少一个实例的IC的物理部分并且生成特定于物理部分的本地时序约束。该方法还可以包括创建IC的物理部分的软件表示。软件表示可以指定本地时序约束和物理部分的shell网表。该方法还可以包括使用软件表示在电路设计的至少一部分上执行定时分析。

2. 发明授权

US07370302B1 Partitioning a large design across multiple devices 有权
标题翻译：在多个设备之间划分大型设计
公开(公告)号：US07370302B1
公开(公告)日：2008-05-06
申请号：US11099887
申请日：2005-04-05
申请人： David A. Knol , Abhishek Ranjan , Salil R. Raje
发明人： David A. Knol , Abhishek Ranjan , Salil R. Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.
摘要翻译：跨多个集成电路划分设计的方法可以包括为多个集成电路中的每一个创建软件结构，并将多个实例分配给所选择的软件构造。多个实例中的每一个可以来自不同的逻辑层级。该方法还可以包括自动地将至少一个输入/输出缓冲器和端口添加到所选择的软件构造以容纳多个实例并且创建连接多个实例的网和所选择的软件中的至少一个输入/输出缓冲器和端口构造。

3. 发明授权

US06286128B1 Method for design optimization using logical and physical information 失效
标题翻译：使用逻辑和物理信息进行设计优化的方法
公开(公告)号：US06286128B1
公开(公告)日：2001-09-04
申请号：US09097299
申请日：1998-06-12
申请人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
发明人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
摘要翻译：提供了使用逻辑和物理信息进行设计优化的方法。在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。该方法可以进一步包括根据第三成本函数优化路由，其中同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。

4. 发明授权

US06775808B1 Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits 有权
标题翻译：用于生成用于设计和制造集成电路的签发原型的方法和装置
公开(公告)号：US06775808B1
公开(公告)日：2004-08-10
申请号：US09632494
申请日：2000-08-03
申请人： Salil R. Raje , Lawrence T. Pileggi , Dinesh D. Gaitonde , Olivier R. Coudert , Padmini Gopalakrishnan , Jackson David Kreiter
发明人： Salil R. Raje , Lawrence T. Pileggi , Dinesh D. Gaitonde , Olivier R. Coudert , Padmini Gopalakrishnan , Jackson David Kreiter
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： Methods and apparatus for a physical “sign-off” prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design. In either situation, the “sign-off” prototype provides a forward prediction of the area, timing and performance of the final GDS of the design generated by a physical implementation tool.
摘要翻译：用于物理“签发”原型工具的方法和设备，包括为设计生成物理原型的原型工具和优化工具，为设计人员提供在进行设计注销之前进一步优化物理原型的选项。在任一情况下，“签署”原型提供了物理实施工具生成的设计的最终GDS的面积，时间和性能的前瞻性预测。

5. 发明授权

US06851099B1 Placement method for integrated circuit design using topo-clustering 有权
标题翻译：使用拓扑聚类的集成电路设计的放置方法
公开(公告)号：US06851099B1
公开(公告)日：2005-02-01
申请号：US09511705
申请日：2000-02-23
申请人： Majid Sarrafzadeh , Salil R. Raje
发明人： Majid Sarrafzadeh , Salil R. Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Initial placement and placement refinement may be performed hierarchically using topocluster trees. A topocluster tree may be used to drive initial placement. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM). In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics-delay, area, congestion, power, etc. During placement refinement using GBFM, cluster size is adjusted iteratively from large to small as determined by horizontal cuts within the topocluster tree. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Topocluster trees may also be used for quadrisection. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.
摘要翻译：本发明一般地提供了一种用于集成电路的物理设计的放置方法，其中在放置过程中发现和利用了自然拓扑特征簇（地形簇）。初始放置和放置细化可以使用顶簇树进行分层执行。可以使用顶层树来驱动初始放置。然后，使用本文称为几何有界FM（GBFM）的技术，随后进行迭代放置细化过程。在GBFM中，FM在本地基础上应用于包含一些数量的分区的窗口。从迭代到迭代，窗口可能会改变位置并且大小变化。当由窗口界定的区域在指定的成本函数方面满足指定的成本阈值时，该区域不参与。成本函数考虑了实际的物理量度 - 延迟，区域，拥塞，功率等。在使用GBFM进行布局优化时，通过顶层树中的水平切割确定了簇大小从大到小的迭代调整。 GBFM发生在递归四分法的上下文中。因此，在GBFM完成之后，执行进一步的四分法步骤，其中每个仓分为四个仓，原始仓的四分之一的门被放置在每个结果仓的中心。然后遵循GBFM，循环重复，直到每个仓包含相当少数量的门。群集树也可用于四次检验。按照上述全局放置过程，电路准备好进行详细的放置，其中将单元格分配给放置行。

6. 发明授权

US06442743B1 Placement method for integrated circuit design using topo-clustering 失效
标题翻译：使用拓扑聚类的集成电路设计的放置方法
公开(公告)号：US06442743B1
公开(公告)日：2002-08-27
申请号：US09097107
申请日：1998-06-12
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.
摘要翻译：本公开描述了用于集成电路的物理设计的放置方法，其中公开了在放置过程期间发现和利用自然拓扑特征簇。拓扑群集驱动初始位置，其中所有的拓扑群集的门最初都放置在放置布局的一个bin或一组位置相关的区域中。使用称为双重几何限幅FM（GBFM）的技术完成迭代放置细化过程。 GBFM在本地基础上应用于包含多个分区的窗口。从迭代到迭代，窗口可能会改变位置并且大小变化。当由窗口界定的区域在指定的成本函数方面满足指定的成本阈值时，该区域停止参与。按照上述全局放置过程，电路准备好进行详细的放置，其中将单元格分配给放置行。

7. 发明授权

US06961916B2 Placement method for integrated circuit design using topo-clustering 有权
公开(公告)号：US06961916B2
公开(公告)日：2005-11-01
申请号：US10136161
申请日：2002-05-01
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

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