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    • 1. 发明授权
    • Timing analysis of a mapped logic design using physical delays
    • 使用物理延迟的映射逻辑设计的时序分析
    • US07886256B1
    • 2011-02-08
    • US12146507
    • 2008-06-26
    • Pradip Kumar JhaDinesh D. GaitondeYau-Tsun Steven Li
    • Pradip Kumar JhaDinesh D. GaitondeYau-Tsun Steven Li
    • G06F17/50G06F9/455
    • G06F17/5031G06F2217/84
    • Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.
    • 公开了用于确定逻辑设计的静态时序分析的方法。 集成电路的多个物理元件的物理延迟弧指定从物理元件的输入到物理元件的输出的相应传播延迟。 逻辑设计的逻辑组件被映射到物理元件的物理组件中的选定的一部分。 对于每个逻辑组件,逻辑延迟弧由物理延迟弧确定。 每个逻辑组件的每个逻辑延迟弧指定从逻辑组件的输入到逻辑组件的输出的传播延迟。 使用逻辑延迟弧执行逻辑组件的静态时序分析,并输出来自定时分析的数据。