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1. 发明授权

US07996752B2 Method and apparatus for decoding a LDPC code 失效
标题翻译：用于对LDPC码进行解码的方法和装置
公开(公告)号：US07996752B2
公开(公告)日：2011-08-09
申请号：US11744860
申请日：2007-05-05
申请人： Abhiram Prabhakar , Yan Zhong
发明人： Abhiram Prabhakar , Yan Zhong
IPC分类号： G06F11/00
CPC分类号： H03M13/1105 , H03M13/6516
摘要： In a decoder for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes, a method is provided. The method comprises the steps of: providing a memory for the decoding with the memory dependent on a parity check matrix H with maximum number of “1”s; using a number of column updating units, updating columns parallely and simultaneously producing messages; and using a number of row updating units, updating rows parallely and simultaneously producing messages. Whereby an improved architecture in a logic and the memory is provided such that an improved throughput, power consumption, and memory area is achieved.
摘要翻译：在用于解码适用于解码多等级LDPC码的低密度奇偶校验（LDPC）码的解码器中，提供了一种方法。该方法包括以下步骤：依赖于具有最大数量“1”的奇偶校验矩阵H提供用于使用存储器进行解码的存储器; 使用多个列更新单元，更新列并行并同时生成消息; 并使用多个行更新单元，并行地并行地生成消息。由此提供了逻辑和存储器中的改进的架构，使得实现了改进的吞吐量，功耗和存储器区域。

2. 发明申请

US20080276151A1 METHOD AND APPARATUS FOR DECODING A LDPC CODE 失效
标题翻译：用于解码LDPC码的方法和装置
公开(公告)号：US20080276151A1
公开(公告)日：2008-11-06
申请号：US11744860
申请日：2007-05-05
申请人： Yan Zhong , Abhiram Prabhakar
发明人： Yan Zhong , Abhiram Prabhakar
IPC分类号： H03M13/05
CPC分类号： H03M13/1105 , H03M13/6516
摘要： In a decoder for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes, a method is provided. The method comprises the steps of: providing a memory for the decoding with the memory dependent on a parity check matrix H with maximum number of “1”s; using a number of column updating units, updating columns parallely and simultaneously producing messages; and using a number of row updating units, updating rows parallely and simultaneously producing messages. Whereby an improved architecture in a logic and the memory is provided such that an improved throughput, power consumption, and memory area is achieved.
摘要翻译：在用于解码适用于解码多等级LDPC码的低密度奇偶校验（LDPC）码的解码器中，提供了一种方法。该方法包括以下步骤：依赖于具有最大数目“1”的奇偶校验矩阵H提供用于使用存储器进行解码的存储器; 使用多个列更新单元，更新列并行并同时生成消息; 并使用多个行更新单元，并行地并行地生成消息。由此提供了逻辑和存储器中的改进的架构，使得实现了改进的吞吐量，功耗和存储器区域。

3. 发明申请

US20080028282A1 RECEIVER ARCHITECTURE HAVING A LDPC DECODER WITH AN IMPROVED LLR UPDATE METHOD FOR MEMORY REDUCTION 审中-公开
标题翻译：具有用于减少存储器的改进的LLR更新方法的LDPC解码器的接收机架构
公开(公告)号：US20080028282A1
公开(公告)日：2008-01-31
申请号：US11557491
申请日：2006-11-07
申请人： Yan Zhong , Abhiram Prabhakar , Dinesh Venkatachalam
发明人： Yan Zhong , Abhiram Prabhakar , Dinesh Venkatachalam
IPC分类号： H03M13/03
CPC分类号： H03M13/116 , H03M13/1102 , H03M13/1114 , H03M13/1117 , H03M13/1122 , H03M13/114 , H03M13/152 , H03M13/251 , H03M13/2732 , H03M13/2906 , H03M13/6505
摘要： The present invention provides a reduced memory implementation for the min-sum algorithm compared to traditional hardware implementations. The improvement includes innovative MIN_SUM method with reduced memory requirements suitable of computer implementation that combines the traditional row update process and column update process into a single process, in that the traditional CNU unit and VNU unit are combined into a single CVNU unit. The improvement not only reduces the time required for decoding by half, but also reduces the logic and routing efforts. Furthermore, instead of storing the whole intermediate LLR values using a significant number of memories, only a set of parameters associated with the intermediate LLR values is stored. The set of parameters includes: 1. sign of LLR; 2. the minimum LLR, 3. sub-minimum LLR, and 4. the column location of minimum value in each row. Therefore, as compared with the traditional LDPC decoder implementation, the required memory size of the present invention is significantly or tremendously reduced.
摘要翻译：与传统硬件实现相比，本发明提供了用于最小和算法的减少的存储器实现。该改进包括创新的MIN_SUM方法，具有较少的内存要求，适合计算机实现，将传统的行更新过程和列更新过程组合到一个过程中，传统的CNU单元和VNU单元组合成一个CVNU单元。该改进不仅将解码所需的时间缩短了一半，而且减少了逻辑和布线工作。此外，代替使用大量存储器存储整个中间LLR值，仅存储与中间LLR值相关联的一组参数。参数集包括：1. LLR的符号; 2.最小LLR，3. sub-minimum LLR和4.每行最小值的列位置。因此，与传统的LDPC解码器实现相比，本发明所需的存储器大小显着或大大降低。

4. 发明授权

US08279593B2 Hard disk retention assembly and electronic device utilizing the same 失效
标题翻译：硬盘保持组件和利用其的电子设备
公开(公告)号：US08279593B2
公开(公告)日：2012-10-02
申请号：US12781992
申请日：2010-05-18
申请人： Jun-Jie Zheng , Yan Zhong , Xin Ji , Wen-Hsiang Hung
发明人： Jun-Jie Zheng , Yan Zhong , Xin Ji , Wen-Hsiang Hung
IPC分类号： G06F1/16 , A47B81/00 , A47F7/00
CPC分类号： G06F1/1601 , G06F1/181 , G06F1/187
摘要： A retention assembly for securing a hard disk to a frame of an electronic device, the retention assembly includes a bracket and a connector. The bracket is fixed to the hard disk. One of the frame and the bracket defining a guide groove, the other one forming a slide rail slidably received in the guide groove. The connector fixed to the frame and adjacent to the guide groove or the slide rail. The hard disk is electrically connected or disconnected to the connector by sliding the bracket along the guide groove or the slide rail.
摘要翻译：一种用于将硬盘固定到电子设备的框架的保持组件，所述保持组件包括支架和连接器。支架固定在硬盘上。框架和支架中的一个限定导向槽，另一个形成滑动地容纳在引导槽中的滑轨。连接器固定在框架上并与导向槽或滑轨相邻。通过沿着引导槽或滑轨滑动托架，硬盘与连接器电连接或断开。

5. 发明授权

US06898757B1 Decoding multi-block product code 失效
标题翻译：解码多块产品代码
公开(公告)号：US06898757B1
公开(公告)日：2005-05-24
申请号：US10117388
申请日：2002-04-04
申请人： Yan Zhong , Lin Yang
发明人： Yan Zhong , Lin Yang
IPC分类号： H03M13/25 , H03M13/29 , H04L1/00 , H04L27/34 , H03M13/03
CPC分类号： H04L1/0057 , H03M13/251 , H03M13/2909 , H04L1/0045 , H04L27/3488
摘要： A method for efficient decoding of block product code format signals, using a (22p)QAM signal constellation for mapping of a received signal, with p=2, 3, 4, 5, . . . A received signal value rx, corresponding to an x=I or x=Q coordinate, is converted to a p-tuple (B(p-1)x, . . . , B0x) corresponding to a “closest” I-coordinate or Q-coordinate numerical value, and a p-stage algorithm is applied to the signal values rx and to the p-tuples (B(p-1)x, . . . , B0x) to determine a p-tuple (r(p-1)x, . . . , r0x) representing a decoded p-bit value for the received signal value rx. Depending upon a communication channel parameter Eb/N0 and the bit error ratio BER associated with each of the p bits, the received signal values rx may be suitable for some or all communications activities (e.g., HDTV, SDTV, mobile comm).
摘要翻译：使用用于映射接收到的信号的（2≤Pp）QAM信号星座来对块产品码格式信号进行有效解码的方法，其中p = 2,3,4,5，...。。。对应于x = I或x = Q坐标的接收信号值r x x x被转换成p元组（B（p-1）x）。对应于“最接近”的I坐标或Q坐标数值的P阶算法，并且将p级算法应用于信号值r x1 / 以及p元组（B＆gt;（p-1）x，...，B×0x））来确定p元组（r∈（p-1） 1）表示用于接收信号值r x x的解码的p位值的x，...，r 。根据通信信道参数Eb / N0和与每个p位相关联的比特误差BER，接收信号值r x x可适用于一些或所有通信活动（例如，HDTV， SDTV，手机通讯）。

6. 发明授权

US5970104A Method and apparatus for generating branch metrics and branch indices for convolutional code Viterbi decoders 失效
标题翻译：用于生成卷积码维特比解码器的分支度量和分支索引的方法和装置
公开(公告)号：US5970104A
公开(公告)日：1999-10-19
申请号：US820922
申请日：1997-03-19
申请人： Yan Zhong , Lin Yang , Manouchehr Rafie
发明人： Yan Zhong , Lin Yang , Manouchehr Rafie
IPC分类号： H03D1/00
CPC分类号： H04L1/0054 , H03M13/395 , H03M13/4107 , H03M13/6508 , H03M13/6561
摘要： A Viterbi decoder generates a branch metric table from first and second data signals taken at two sample times and provides selected branch metrics to an add/compare/select circuit in response to branch indices from a branch index generator. The branch metrics in the branch metric table are the sixteen combinations of the sum of the first and second parallel data signals at first and second sample times and the inverse of such signals. The branch index generator generates the branch indices in response to a received state from the add/compare/select circuit, convolutional code polynomials and the possible states of a radix-4 trellis. The add/compare/select generates a survivor path decision based on the selected branch metrics.
摘要翻译：维特比解码器从在两个采样时间获取的第一和第二数据信号产生分支度量表，并且响应于来自分支索引发生器的分支索引将选择的分支度量提供给加法/比较/选择电路。分支度量表中的分支度量是第一和第二采样时间的第一和第二并行数据信号之和与这些信号的倒数的十六个组合。分支索引生成器响应于来自加法/比较/选择电路的接收状态，卷积码多项式和基数-4格子的可能状态产生分支索引。添加/比较/选择基于所选择的分支度量生成幸存者路径决策。

7. 发明授权

US09013106B2 Lamp ballast having filament heating apparatus for gas discharge lamp 有权
标题翻译：具有气体放电灯灯丝加热装置的灯具镇流器
公开(公告)号：US09013106B2
公开(公告)日：2015-04-21
申请号：US13242170
申请日：2011-09-23
申请人： Weiqiang Zhang , Qi Zhang , Yan Zhong , Ching-Ho Chou , Jianping Ying
发明人： Weiqiang Zhang , Qi Zhang , Yan Zhong , Ching-Ho Chou , Jianping Ying
IPC分类号： H01J13/32 , H05B41/295
CPC分类号： H05B41/295
摘要： Provided is a lamp ballast having a filament heating apparatus for gas discharge lamp, including a PFC converter for receiving an AC input voltage and converting the AC input voltage into a DC bus voltage; an inverter connected to an output end of the PFC converter for converting the DC bus voltage into an AC output voltage for driving gas discharge lamps; and a filament heating apparatus connected to the output end of the PFC converter. The filament heating apparatus includes an auxiliary heating circuit for converting the DC bus voltage into a heating power for pre-heating the filaments of the gas discharge lamps; and a control circuit connected to the inverter and the auxiliary heating circuit for generating an auxiliary voltage according to the heating power to activate the PFC converter. After the auxiliary heating circuit has been operating for a predetermined period of time, the auxiliary heating circuit is turned off first and then the inverter is turned on; or otherwise the inverter is turned on first and then the auxiliary heating circuit is turned off.
摘要翻译：提供一种具有用于气体放电灯的灯丝加热装置的灯镇流器，包括用于接收AC输入电压并将AC输入电压转换成DC总线电压的PFC转换器; 连接到PFC转换器的输出端的逆变器，用于将DC总线电压转换成用于驱动气体放电灯的AC输出电压; 以及连接到PFC转换器的输出端的灯丝加热装置。灯丝加热装置包括辅助加热电路，用于将直流母线电压转换成用于对气体放电灯的细丝进行预热的加热功率; 以及连接到逆变器和辅助加热电路的控制电路，用于根据加热功率产生辅助电压以激活PFC转换器。在辅助加热电路已经运行预定时间段之后，首先关闭辅助加热电路，然后使逆变器接通; 否则逆变器首先接通，然后辅助加热电路关闭。

8. 发明授权

US08917035B2 Voltage regulation circuit and light emitting didoe driving apparatus having the same 有权
标题翻译：电压调节电路和具有该电压调节电路的发光飞镖驱动装置
公开(公告)号：US08917035B2
公开(公告)日：2014-12-23
申请号：US13541680
申请日：2012-07-04
申请人： Wei-Qiang Zhang , Yan Zhong , Jian-Ping Ying
发明人： Wei-Qiang Zhang , Yan Zhong , Jian-Ping Ying
IPC分类号： G05F1/00 , H05B37/02 , H05B39/04 , H05B41/36
CPC分类号： H05B37/02 , H05B33/0812 , H05B33/0815 , H05B33/0827 , Y02B20/345 , Y02B20/347
摘要： A voltage regulation circuit includes a voltage conversion module, an LED driving module and a control module. The voltage conversion module is operable to receive and convert the first voltage to a second voltage. Each LED driving loop of the LED driving module has a current regulator and an LED string. The control module is operable to output a control signal according to the received input signal which reflects the current flowing through the LED driving module. The voltage conversion module regulates the second voltage according to the control signal, such that the regulated second voltage still keeps the brightness of the LED string of each LED driving loop unchanged.
摘要翻译：电压调节电路包括电压转换模块，LED驱动模块和控制模块。电压转换模块可操作以接收第一电压并将其转换为第二电压。 LED驱动模块的每个LED驱动环路具有电流调节器和LED串。控制模块可操作以根据接收到的反映流过LED驱动模块的电流的输入信号输出控制信号。电压转换模块根据控制信号调节第二电压，使得调节的第二电压仍保持每个LED驱动环路的LED串的亮度不变。

9. 发明授权

US08742670B2 Electronic ballast 有权
标题翻译：电子镇流器
公开(公告)号：US08742670B2
公开(公告)日：2014-06-03
申请号：US13530380
申请日：2012-06-22
申请人： Yan Zhong , Weiqiang Zhang , JianPing Ying
发明人： Yan Zhong , Weiqiang Zhang , JianPing Ying
IPC分类号： H05B41/36 , H01J61/52
CPC分类号： H05B41/2828 , H05B41/3927
摘要： The electronic ballast includes: a square wave generator that includes a plurality of switching elements to convert a DC input voltage to an AC square wave output voltage; a transformer that includes a driving winding, a plurality of control windings, at least one inductive winding and at least one control driving circuit. The control windings controls the plurality of switching elements to turn on alternately; a resonant circuit that constitutes a resonant loop together with the driving winding is electrically connected with an output terminal of the square wave generator to drive the light emitting element. The control driving circuit is connected with two terminals of the inductive winding in parallel and receives a control signal to control a voltage across the inductive winding so as to control conducting time of at least one of the switching elements.
摘要翻译：电子镇流器包括：方波发生器，其包括将DC输入电压转换为AC方波输出电压的多个开关元件; 包括驱动绕组，多个控制绕组，至少一个感应绕组和至少一个控制驱动电路的变压器。控制绕组控制多个开关元件交替地接通; 与驱动绕组一起构成谐振回路的谐振电路与方波发生器的输出端电连接，驱动发光元件。控制驱动电路并联连接电感线圈的两个端子，并接收控制信号以控制感应绕组两端的电压，以控制至少一个开关元件的导通时间。

10. 发明申请

US20120313527A1 LAMP BALLAST HAVING FILAMENT HEATING APPARATUS FOR GAS DISCHARGE LAMP 有权
标题翻译：具有气体放电灯的灯泡加热装置的灯管
公开(公告)号：US20120313527A1
公开(公告)日：2012-12-13
申请号：US13242170
申请日：2011-09-23
申请人： Weiqiang Zhang , Qi Zhang , Yan Zhong , Ching-Ho Chou , Jianping Ying
发明人： Weiqiang Zhang , Qi Zhang , Yan Zhong , Ching-Ho Chou , Jianping Ying
IPC分类号： H05B41/08
CPC分类号： H05B41/295
摘要： Provided is a lamp ballast having a filament heating apparatus for gas discharge lamp, including a PFC converter for receiving an AC input voltage and converting the AC input voltage into a DC bus voltage; an inverter connected to an output end of the PFC converter for converting the DC bus voltage into an AC output voltage for driving gas discharge lamps; and a filament heating apparatus connected to the output end of the PFC converter. The filament heating apparatus includes an auxiliary heating circuit for converting the DC bus voltage into a heating power for pre-heating the filaments of the gas discharge lamps; and a control circuit connected to the inverter and the auxiliary heating circuit for generating an auxiliary voltage according to the heating power to activate the PFC converter. After the auxiliary heating circuit has been operating for a predetermined period of time, the auxiliary heating circuit is turned off first and then the inverter is turned on; or otherwise the inverter is turned on first and then the auxiliary heating circuit is turned off.
摘要翻译：提供一种具有用于气体放电灯的灯丝加热装置的灯镇流器，包括用于接收AC输入电压并将AC输入电压转换成DC总线电压的PFC转换器; 连接到PFC转换器的输出端的逆变器，用于将DC总线电压转换成用于驱动气体放电灯的AC输出电压; 以及连接到PFC转换器的输出端的灯丝加热装置。灯丝加热装置包括辅助加热电路，用于将直流母线电压转换成用于对气体放电灯的细丝进行预热的加热功率; 以及连接到逆变器和辅助加热电路的控制电路，用于根据加热功率产生辅助电压以激活PFC转换器。在辅助加热电路已经运行预定时间段之后，首先关闭辅助加热电路，然后使逆变器接通; 否则逆变器首先接通，然后辅助加热电路关闭。

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