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1. 发明申请

WO2012083012A8 DEVICE DISCOVERY AND TOPOLOGY REPORTING IN A COMBINED CPU/GPU ARCHITECTURE SYSTEM 审中-公开
标题翻译：组合式CPU / GPU架构系统中的器件发现和拓扑报告
公开(公告)号：WO2012083012A8
公开(公告)日：2012-10-04
申请号：PCT/US2011065136
申请日：2011-12-15
申请人： ADVANCED MICRO DEVICES INC , ATI TECHNOLOGIES ULC , BLINZER PAUL , VAN DOORN LEENDERT , CHENG JEFFREY , TERRY ELENE , WOLLER THOMAS , RAHMAN ARSHAD
发明人： BLINZER PAUL , VAN DOORN LEENDERT , CHENG JEFFREY , TERRY ELENE , WOLLER THOMAS , RAHMAN ARSHAD
IPC分类号： G06F9/46
CPC分类号： E21B4/14
摘要： Methods and apparatus are provided, as an aspect of a combined CPU/ APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/ APD architecture system. The combined CPU/ APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/ APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.
摘要翻译：作为组合CPU / APD体系结构系统的一个方面，提供了用于发现和报告与有效调度和分配计算任务到组合的CPU / APD体系结构的各种计算资源相关的设备和系统拓扑的属性的方法和装置系统。组合的CPU / APD架构在灵活的计算环境中统一了CPU和APD。在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。组合的CPU / APD架构为现有的和新的编程框架，语言和工具构建奠定了基础。

2. 发明申请

WO2011109613A3 METHOD, SYSTEM, AND APPARATUS FOR PROCESSING VIDEO AND/OR GRAPHICS DATA USING MULTIPLE PROCESSORS WITHOUT LOSING STATE INFORMATION 审中-公开
标题翻译：使用多个处理器处理视频和/或图形数据的方法，系统和设备，而不会丢失状态信息
公开(公告)号：WO2011109613A3
公开(公告)日：2011-11-17
申请号：PCT/US2011027019
申请日：2011-03-03
申请人： ATI TECHNOLOGIES ULC , BLINZER PAUL
发明人： BLINZER PAUL
IPC分类号： G06F9/48 , G06F1/32 , G06F9/50 , G06T15/00 , G09G5/36
CPC分类号： G06F9/5011 , G06F1/3203 , G06F2209/507 , G06T1/20 , G09G5/363 , G09G2330/021 , G09G2360/06
摘要： Method, system, and apparatus provides for the processing of video and/or graphics data using a combination of first graphics processing circuitry and second graphics processing circuitry without losing state information while transferring the processing between the first and second graphics processing circuitry. The video and/or graphics data to be processed may be, for example, supplied by an application running on a processor such as host processor. In one example, an apparatus includes at least one GPU that includes a plurality of single instruction multiple data (SEVID) execution units. The GPU is operative to execute a native function code module. The apparatus also includes at least a second GPU that includes a plurality of SEVID execution units having a same programming model as the plurality of SEVID execution units on the first GPU. Furthermore, the first and second GPUs are operative to execute the same native function code module. The native code function module causes the first GPU to provide state information for the at least second GPU in response to a notification from a first processor, such as a host processor, that a transition from a current operational mode to a desired operational mode is desired (e.g., one GPU is stopped and the other GPU is started). The second GPU is operative to obtain the state information provided by the first GPU and use the state information via the same native function code module to continue processing where the first GPU left off. The first processor is operatively coupled to the at least first and at least second GPUs.
摘要翻译：方法，系统和装置使用第一图形处理电路和第二图形处理电路的组合来处理视频和/或图形数据，而不会在第一和第二图形处理电路之间转移处理时丢失状态信息。要处理的视频和/或图形数据可以例如由在诸如主机处理器的处理器上运行的应用程序提供。在一个示例中，装置包括至少一个GPU，其包括多个单指令多数据（SEVID）执行单元。 GPU可操作来执行本地功能代码模块。该装置还包括至少第二GPU，其包括具有与第一GPU上的多个SEVID执行单元相同的编程模型的多个SEVID执行单元。此外，第一和第二GPU可操作以执行相同的本机功能代码模块。本地代码功能模块使得第一GPU响应于来自诸如主机处理器的第一处理器的通知而提供至少第二GPU的状态信息，期望从当前操作模式转换到期望的操作模式（例如，一个GPU停止，另一个GPU启动）。第二GPU可操作以获得由第一GPU提供的状态信息，并通过相同的本地功能代码模块使用状态信息来继续处理第一GPU离开的处理。第一处理器可操作地耦合到至少第一和至少第二GPU。

3. 发明申请

WO2013090594A8 INFRASTRUCTURE SUPPORT FOR GPU MEMORY PAGING WITHOUT OPERATING SYSTEM INTEGRATION 审中-公开
标题翻译：基于GPU的内存支持基础架构支持，无需运行系统集成
公开(公告)号：WO2013090594A8
公开(公告)日：2014-05-15
申请号：PCT/US2012069531
申请日：2012-12-13
申请人： ADVANCED MICRO DEVICES INC , ATI TECHNOLOGIES ULC
发明人： WOLLER THOMAS ROY , VAN DOORN LEENDERT PETER , RAHMAN ARSHAD , BLINZER PAUL , CHENG GONGXIAN JEFFREY , TERRY ELENE
IPC分类号： G06F9/38 , G06F9/30 , G06F12/10
CPC分类号： G06F12/1009 , G06F9/3004 , G06F9/3881 , G06F2009/3883 , G06F2212/683
摘要： In a CPU of the combined CPU/GPU architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to a GPU, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 Page Table invalidations.
摘要翻译：在组合的CPU / GPU架构系统的CPU中，CPU具有多个CPU核心，每个核心具有用于接收物理页面/页面目录基址的第一机器特定寄存器，用于接收物理地址指向到由通信地耦合到GPU的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制已经更新了CPU核心的寄存器，并且响应于控制寄存器已被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中，物理地址能够接收影响IOMMUv2 Page表无效的写入。

4. 发明公开

EP2652611A4 DEVICE DISCOVERY AND TOPOLOGY REPORTING IN A COMBINED CPU/GPU ARCHITECTURE SYSTEM 审中-公开
标题翻译： VORRICHTUNGSERKENNUNG UND TOPOLOGIEBERICHTERSTATTUNG在EINEM KOMBINIERTEN CPU / GPU-ARCHITEKTURSYSTEM
公开(公告)号：EP2652611A4
公开(公告)日：2017-04-26
申请号：EP11847935
申请日：2011-12-15
申请人： ADVANCED MICRO DEVICES INC , ATI TECHNOLOGIES ULC
发明人： BLINZER PAUL , VAN DOORN LEENDERT , CHENG JEFFREY , TERRY ELENE , WOLLER THOMAS , RAHMAN ARSHAD
IPC分类号： G06F9/46 , G06F9/30 , G06F15/76 , G06T1/20
CPC分类号： G06T1/20 , G06F9/30003
摘要： Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.
摘要翻译：作为组合CPU / APD体系结构系统的一个方面，提供了用于发现和报告与有效调度和分配计算任务到组合的CPU / APD体系结构的各种计算资源相关的设备和系统拓扑的属性的方法和装置系统。组合的CPU / APD架构在灵活的计算环境中统一了CPU和APD。在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。组合的CPU / APD架构为现有的和新的编程框架，语言和工具构建奠定了基础。

5. 发明申请

WO2009076671A3 DRIVER ARCHITECTURE FOR COMPUTING DEVICE HAVING MULTIPLE GRAPHICS SUBSYSTEMS, REDUCED POWER CONSUMPTION MODES, SOFTWARE AND METHODS 审中-公开
标题翻译：用于具有多个图形子系统的计算设备的驱动器架构，降低的功耗模式，软件和方法
公开(公告)号：WO2009076671A3
公开(公告)日：2009-07-30
申请号：PCT/US2008086835
申请日：2008-12-15
申请人： ADVANCED MICRO DEVICES INC , MUMMAH PHIL , BLINZER PAUL
发明人： BLINZER PAUL
IPC分类号： G06F9/445 , G06F9/48
CPC分类号： G06F1/3203 , G06F1/3265 , G06F1/3293 , G09G5/12 , G09G5/363 , G09G2330/022 , G09G2340/0435 , G09G2360/06 , G09G2370/04 , Y02D10/122 , Y02D10/153
摘要： Many computing devices may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities and may, for example, consume differing amounts of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems. A further proxy driver component routes calls (e.g. API/DDI calls) to one of said first and second driver components, in dependence on which of the first and second graphics system is in use.
摘要翻译：现在许多计算设备可能包括两个或更多图形子系统。多个图形子系统可以具有不同的能力，并且例如可以消耗不同数量的电力，其中一个子系统消耗比其他子系统更多的平均功率。较高功耗的图形子系统可以耦合到该设备并且代替或者除了较低功耗的图形子系统之外使用，从而导致更高的性能或附加能力，但是增加了整体功耗。通过从使用较高功耗的图形子系统转换到较低功耗的图形子系统，将较高功耗的图形子系统置于较低的功耗模式，可降低整体功耗。处理器执行应用软件和驱动程序软件。驱动器软件包括用于分别控制第一和第二图形子系统的操作的第一和第二驱动器组件。另一个代理驱动程序组件根据第一和第二图形系统中的哪一个正在使用将呼叫（例如API / DDI调用）路由到所述第一和第二驱动程序组件之一。

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