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1. 发明申请

WO2012083012A8 DEVICE DISCOVERY AND TOPOLOGY REPORTING IN A COMBINED CPU/GPU ARCHITECTURE SYSTEM 审中-公开
标题翻译：组合式CPU / GPU架构系统中的器件发现和拓扑报告
公开(公告)号：WO2012083012A8
公开(公告)日：2012-10-04
申请号：PCT/US2011065136
申请日：2011-12-15
申请人： ADVANCED MICRO DEVICES INC , ATI TECHNOLOGIES ULC , BLINZER PAUL , VAN DOORN LEENDERT , CHENG JEFFREY , TERRY ELENE , WOLLER THOMAS , RAHMAN ARSHAD
发明人： BLINZER PAUL , VAN DOORN LEENDERT , CHENG JEFFREY , TERRY ELENE , WOLLER THOMAS , RAHMAN ARSHAD
IPC分类号： G06F9/46
CPC分类号： E21B4/14
摘要： Methods and apparatus are provided, as an aspect of a combined CPU/ APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/ APD architecture system. The combined CPU/ APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/ APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.
摘要翻译：作为组合CPU / APD体系结构系统的一个方面，提供了用于发现和报告与有效调度和分配计算任务到组合的CPU / APD体系结构的各种计算资源相关的设备和系统拓扑的属性的方法和装置系统。组合的CPU / APD架构在灵活的计算环境中统一了CPU和APD。在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。组合的CPU / APD架构为现有的和新的编程框架，语言和工具构建奠定了基础。

2. 发明申请

WO2013090594A8 INFRASTRUCTURE SUPPORT FOR GPU MEMORY PAGING WITHOUT OPERATING SYSTEM INTEGRATION 审中-公开
标题翻译：基于GPU的内存支持基础架构支持，无需运行系统集成
公开(公告)号：WO2013090594A8
公开(公告)日：2014-05-15
申请号：PCT/US2012069531
申请日：2012-12-13
申请人： ADVANCED MICRO DEVICES INC , ATI TECHNOLOGIES ULC
发明人： WOLLER THOMAS ROY , VAN DOORN LEENDERT PETER , RAHMAN ARSHAD , BLINZER PAUL , CHENG GONGXIAN JEFFREY , TERRY ELENE
IPC分类号： G06F9/38 , G06F9/30 , G06F12/10
CPC分类号： G06F12/1009 , G06F9/3004 , G06F9/3881 , G06F2009/3883 , G06F2212/683
摘要： In a CPU of the combined CPU/GPU architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to a GPU, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 Page Table invalidations.
摘要翻译：在组合的CPU / GPU架构系统的CPU中，CPU具有多个CPU核心，每个核心具有用于接收物理页面/页面目录基址的第一机器特定寄存器，用于接收物理地址指向到由通信地耦合到GPU的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制已经更新了CPU核心的寄存器，并且响应于控制寄存器已被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中，物理地址能够接收影响IOMMUv2 Page表无效的写入。

3. 发明公开

EP2652611A4 DEVICE DISCOVERY AND TOPOLOGY REPORTING IN A COMBINED CPU/GPU ARCHITECTURE SYSTEM 审中-公开
标题翻译： VORRICHTUNGSERKENNUNG UND TOPOLOGIEBERICHTERSTATTUNG在EINEM KOMBINIERTEN CPU / GPU-ARCHITEKTURSYSTEM
公开(公告)号：EP2652611A4
公开(公告)日：2017-04-26
申请号：EP11847935
申请日：2011-12-15
申请人： ADVANCED MICRO DEVICES INC , ATI TECHNOLOGIES ULC
发明人： BLINZER PAUL , VAN DOORN LEENDERT , CHENG JEFFREY , TERRY ELENE , WOLLER THOMAS , RAHMAN ARSHAD
IPC分类号： G06F9/46 , G06F9/30 , G06F15/76 , G06T1/20
CPC分类号： G06T1/20 , G06F9/30003
摘要： Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.
摘要翻译：作为组合CPU / APD体系结构系统的一个方面，提供了用于发现和报告与有效调度和分配计算任务到组合的CPU / APD体系结构的各种计算资源相关的设备和系统拓扑的属性的方法和装置系统。组合的CPU / APD架构在灵活的计算环境中统一了CPU和APD。在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。组合的CPU / APD架构为现有的和新的编程框架，语言和工具构建奠定了基础。

4. 发明申请

WO2013090594A3 INFRASTRUCTURE SUPPORT FOR GPU MEMORY PAGING WITHOUT OPERATING SYSTEM INTEGRATION 审中-公开
标题翻译：基于基础架构的GPU存储器寻址支持，无需操作系统集成
公开(公告)号：WO2013090594A3
公开(公告)日：2013-12-19
申请号：PCT/US2012069531
申请日：2012-12-13
申请人： ADVANCED MICRO DEVICES INC
发明人： WOLLER THOMAS ROY , VAN DOORN LEENDERT PETER , RAHMAN ARSHAD , BLINZER PAUL , CHENG GONGXIAN JEFFREY , TERRY ELENE
IPC分类号： G06F9/38 , G06F9/30 , G06F12/10
CPC分类号： G06F12/1009 , G06F9/3004 , G06F9/3881 , G06F2009/3883 , G06F2212/683
摘要： In a CPU of the combined CPU/GPU architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to a GPU, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 Page Table invalidations.
摘要翻译：在组合CPU / GPU架构系统的CPU中，CPU具有多个CPU核心，每个核心具有用于接收物理页面/页面目录基地址的第一机器专用寄存器，用于接收物理地址指针的第二机器专用寄存器到由通信地耦合到GPU的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器专用寄存器中的物理地址发出写入通知的微码; 在CPU核心的第一机器专用寄存器中接收物理页面表/页面目录基地址，在CPU核心的第二机器专用寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制器 CPU核心的寄存器已经被更新，并且响应于确定控制寄存器已被更新，执行CPU核心中的微码，该微码导致写入通知被发送到包含在第二机器专用寄存器中的物理地址，其中，物理地址能够接收影响IOMMUv2页表失效的写入。

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