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1. 发明申请

WO2007093906A1 DYNAMIC BUS INVERSION METHOD AND SYSTEM 审中-公开
标题翻译：动态总线反相方法与系统
公开(公告)号：WO2007093906A1
公开(公告)日：2007-08-23
申请号：PCT/IB2007/000381
申请日：2007-02-16
申请人： ATI TECHNOLOGIES, INC , ATI INTERNATIONAL SRL , MACRI, Joseph , MOREIN, Stephen, L. , LEE, Edward (Ming-Ju) , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen, L. , LEE, Edward (Ming-Ju) , CHEN, Lin
IPC分类号： H04L25/49 , G06F13/42
CPC分类号： H04L25/4915 , H03L7/07 , H03L7/0805 , H03L7/0814 , H04L7/0004 , H04L7/0008 , H04L7/0037 , H04L7/0337
摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.
摘要翻译：描述了动态总线反演（DBI）方法和系统。在各种实施例中，发射机通过多比特高速总线向接收机发送数据。在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。接收器接收并解码DBI信号，并且作为响应，适当地解码所接收的数据。

2. 发明申请

WO2007096769A1 WRITE DATA MASK METHOD AND SYSTEM 审中-公开
标题翻译：写数据掩码方法和系统
公开(公告)号：WO2007096769A1
公开(公告)日：2007-08-30
申请号：PCT/IB2007/000467
申请日：2007-02-20
申请人： ATI TECHNOLOGIES, INC , ATI INTERNATIONAL SRL , MACRI, Joseph , MOREIN, Stephen, L. , LEE, Edward , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen, L. , LEE, Edward , CHEN, Lin
IPC分类号： G06F13/42
CPC分类号： G06F12/00 , G06F13/4234 , G06F13/4243 , G11C7/02 , G11C7/1006 , G11C7/1078 , G11C7/1096
摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.
摘要翻译：描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。不使用专用的掩码引脚或专用掩码线。在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。在一个实施例中，掩模数据作为写入命令的一部分被发送。

3. 发明申请

WO2007117526A2 LOW POWER MODE UNIPOLAR CURRENT/VOLTAGE MODE INTERFACE 审中-公开
标题翻译：低功耗模式单极电流/电压模式界面
公开(公告)号：WO2007117526A2
公开(公告)日：2007-10-18
申请号：PCT/US2007/008438
申请日：2007-04-03
申请人： ATI TECHNOLOGIES, INC. , ATI INTERNATIONAL SRL , MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-ju, E. , MOREIN, Stephen , CHEN, Lin
发明人： MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-ju, E. , MOREIN, Stephen , CHEN, Lin
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.
摘要翻译：描述用于存储器接口的功耗降低过程的实施例。电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

4. 发明申请

WO2007015915A1 BIT-DESKEWING IO METHOD AND SYSTEM 审中-公开
标题翻译： BIT-DESKEWING IO方法和系统
公开(公告)号：WO2007015915A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/028092
申请日：2006-07-19
申请人： ATI TECHNOLOGIES, INC. , LEE, Edward , BOMDICA, Arvind , CHEN, Lin , GAUTHIER, Claude , HUYNH, Sam , NG, Hiok-Tiaq , LING, John , HO, Jennifer , M.K., Siji , YEE, Gin , MACRI, Joseph
发明人： LEE, Edward , BOMDICA, Arvind , CHEN, Lin , GAUTHIER, Claude , HUYNH, Sam , NG, Hiok-Tiaq , LING, John , HO, Jennifer , M.K., Siji , YEE, Gin , MACRI, Joseph
IPC分类号： H04L7/033
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H04L7/0004 , H04L7/0037 , H04L7/0337
摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.
摘要翻译：描述了用于位移校正的IO方法和系统。实施例包括具有在其间传送数据的多个组件的计算机系统。在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。接收组件包括可选择对准正向选通采样时钟的正向选通时钟恢复电路，以便提高采样精度。接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以便提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪系统运行期间的正向选通采样时钟。

5. 发明申请

WO2007040734A1 COMMUNICATING CLIENT PHASE INFORMATION IN AN IO SYSTEM 审中-公开
标题翻译：在IO系统中通信客户端相位信息
公开(公告)号：WO2007040734A1
公开(公告)日：2007-04-12
申请号：PCT/US2006/028749
申请日：2006-07-25
申请人： ATI TECHNOLOGIES, INC. , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L7/033 , H04L7/00 , G06F1/10 , H03L7/081
CPC分类号： G06F1/04 , G06F1/10 , H04L7/0012 , H04L7/033
摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.
摘要翻译：描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间发送的。

6. 发明申请

WO2007136785A2 FAST TRANSITION FROM LOW-SPEED MODE TO HIGH-SPEED MODE IN HIGH-SPEED INTERFACES 审中-公开
标题翻译：从高速模式到高速接口的高速模式的快速切换
公开(公告)号：WO2007136785A2
公开(公告)日：2007-11-29
申请号：PCT/US2007/011964
申请日：2007-05-17
申请人： ATI TECHNOLOGIES, INC. , MACRI, Joseph , MOREIN, Stephen , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , LEE, Ming-Ju, E. , CHEN, Lin
CPC分类号： G06F1/3275 , G06F1/3225 , G11C7/1045 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2227 , Y02D10/14
摘要： Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high¬ speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.
摘要翻译：描述了针对在模拟定时电路初始化和变得可用的时间段期间继续以低功率模式工作的存储器件和存储器控制器的实施例。在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行模式。参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由从低速模式向高速模式的转变将大大降低。

7. 发明申请

WO2007035345A1 ASYMMETRICAL IO METHOD AND SYSTEM 审中-公开
标题翻译：不对称IO方法和系统
公开(公告)号：WO2007035345A1
公开(公告)日：2007-03-29
申请号：PCT/US2006/035627
申请日：2006-09-13
申请人： ATI TECHNOLOGIES, INC. , MOREIN, Stephen , MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MOREIN, Stephen , MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L7/00 , G06F13/42
CPC分类号： H04L7/02 , H04L7/0025 , H04L7/0091
摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
摘要翻译：描述了非对称IO方法和系统。在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。共享资源包括一个共享相位内插器。在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

8. 发明申请

WO2007058748A1 PROGRAMMABLE PREAMBLE SYSTEM AND METHOD 审中-公开
标题翻译：可编程序系统和方法
公开(公告)号：WO2007058748A1
公开(公告)日：2007-05-24
申请号：PCT/US2006/041855
申请日：2006-10-24
申请人： ATI TECHNOLOGIES, INC. , MACRI, Joseph , FRANKOVICH, Mark
发明人： MACRI, Joseph , FRANKOVICH, Mark
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G06F13/1689 , G11C7/20
摘要： A system includes a first communication device and a second communication device. The first communication device includes a programmable region. The programmable region of the first communication device is programmed so that an associated signal includes a number of preamble cycles. The second communication device also can include a programmable region. The programmable region of the second communication device can be programmed so that an associated signal includes a number of preamble cycles. The number of preamble cycles can be based on a variety of factors, such as the topology or implementation of the system. In an embodiment, the number of preamble cycles is associated with a data strobe signal, and data is not read or written in response to the data strobe signal until all of the preamble cycles have been transmitted and received.
摘要翻译：系统包括第一通信设备和第二通信设备。第一通信设备包括可编程区域。对第一通信设备的可编程区域进行编程，使得相关联的信号包括多个前导码周期。第二通信设备还可以包括可编程区域。可以对第二通信设备的可编程区域进行编程，使得相关联的信号包括多个前导码周期。前导码周期的数量可以基于各种因素，例如系统的拓扑或实现。在一个实施例中，前导码周期的数量与数据选通信号相关联，并且数据不是响应于数据选通信号而被读取或写入，直到已经发送和接收所有前导码周期为止。

9. 发明申请

WO2007054808A2 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES 审中-公开
标题翻译：高速不对称接口中使用专用接口线的误差检测
公开(公告)号：WO2007054808A2
公开(公告)日：2007-05-18
申请号：PCT/IB2006/003180
申请日：2006-11-10
申请人： ADVANCED MICRO DEVICES, INC , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L1/00 , G06F11/08
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速不对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件明显比第二组件更智能。第一个组件通过接口的一行接收来自第二个组件的签名，并通过该接口进行READ和WRITE操作。与从第二组件到第一组件签名的传输相关联的等待时间是第二组件计算签名所用的时间。将收到的签名与第一个组件存储的签名进行比较。这两个签名都对应于特定的READ或WRITE命令。基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

10. 发明申请

WO2007052147A3 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES 审中-公开
公开(公告)号：WO2007052147A3
公开(公告)日：2007-05-10
申请号：PCT/IB2006/003113
申请日：2006-11-02
申请人： ADVANCED MICRO DEVICES, INC. , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

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