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1. 发明申请

WO2007054808A2 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES 审中-公开
标题翻译：高速不对称接口中使用专用接口线的误差检测
公开(公告)号：WO2007054808A2
公开(公告)日：2007-05-18
申请号：PCT/IB2006/003180
申请日：2006-11-10
申请人： ADVANCED MICRO DEVICES, INC , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L1/00 , G06F11/08
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速不对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件明显比第二组件更智能。第一个组件通过接口的一行接收来自第二个组件的签名，并通过该接口进行READ和WRITE操作。与从第二组件到第一组件签名的传输相关联的等待时间是第二组件计算签名所用的时间。将收到的签名与第一个组件存储的签名进行比较。这两个签名都对应于特定的READ或WRITE命令。基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

2. 发明申请

WO2007052147A3 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES 审中-公开
公开(公告)号：WO2007052147A3
公开(公告)日：2007-05-10
申请号：PCT/IB2006/003113
申请日：2006-11-02
申请人： ADVANCED MICRO DEVICES, INC. , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

3. 发明申请

WO2007040734A1 COMMUNICATING CLIENT PHASE INFORMATION IN AN IO SYSTEM 审中-公开
标题翻译：在IO系统中通信客户端相位信息
公开(公告)号：WO2007040734A1
公开(公告)日：2007-04-12
申请号：PCT/US2006/028749
申请日：2006-07-25
申请人： ATI TECHNOLOGIES, INC. , MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L7/033 , H04L7/00 , G06F1/10 , H03L7/081
CPC分类号： G06F1/04 , G06F1/10 , H04L7/0012 , H04L7/033
摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.
摘要翻译：描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间发送的。

4. 发明申请

WO2007117526A2 LOW POWER MODE UNIPOLAR CURRENT/VOLTAGE MODE INTERFACE 审中-公开
标题翻译：低功耗模式单极电流/电压模式界面
公开(公告)号：WO2007117526A2
公开(公告)日：2007-10-18
申请号：PCT/US2007/008438
申请日：2007-04-03
申请人： ATI TECHNOLOGIES, INC. , ATI INTERNATIONAL SRL , MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-ju, E. , MOREIN, Stephen , CHEN, Lin
发明人： MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-ju, E. , MOREIN, Stephen , CHEN, Lin
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.
摘要翻译：描述用于存储器接口的功耗降低过程的实施例。电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

5. 发明申请

WO2007035345A1 ASYMMETRICAL IO METHOD AND SYSTEM 审中-公开
标题翻译：不对称IO方法和系统
公开(公告)号：WO2007035345A1
公开(公告)日：2007-03-29
申请号：PCT/US2006/035627
申请日：2006-09-13
申请人： ATI TECHNOLOGIES, INC. , MOREIN, Stephen , MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
发明人： MOREIN, Stephen , MACRI, Joseph , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L7/00 , G06F13/42
CPC分类号： H04L7/02 , H04L7/0025 , H04L7/0091
摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
摘要翻译：描述了非对称IO方法和系统。在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。共享资源包括一个共享相位内插器。在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

6. 发明申请

WO2007015915A1 BIT-DESKEWING IO METHOD AND SYSTEM 审中-公开
标题翻译： BIT-DESKEWING IO方法和系统
公开(公告)号：WO2007015915A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/028092
申请日：2006-07-19
申请人： ATI TECHNOLOGIES, INC. , LEE, Edward , BOMDICA, Arvind , CHEN, Lin , GAUTHIER, Claude , HUYNH, Sam , NG, Hiok-Tiaq , LING, John , HO, Jennifer , M.K., Siji , YEE, Gin , MACRI, Joseph
发明人： LEE, Edward , BOMDICA, Arvind , CHEN, Lin , GAUTHIER, Claude , HUYNH, Sam , NG, Hiok-Tiaq , LING, John , HO, Jennifer , M.K., Siji , YEE, Gin , MACRI, Joseph
IPC分类号： H04L7/033
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H04L7/0004 , H04L7/0037 , H04L7/0337
摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.
摘要翻译：描述了用于位移校正的IO方法和系统。实施例包括具有在其间传送数据的多个组件的计算机系统。在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。接收组件包括可选择对准正向选通采样时钟的正向选通时钟恢复电路，以便提高采样精度。接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以便提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪系统运行期间的正向选通采样时钟。

7. 发明公开

EP1955467A2 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES 审中-公开
标题翻译：快速，非对称接口错误检测使用特殊的接口线
公开(公告)号：EP1955467A2
公开(公告)日：2008-08-13
申请号：EP06809206.3
申请日：2006-11-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： H04L1/00 , G06F11/08
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

8. 发明公开

EP1955163A2 ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES 审中-公开
标题翻译： SCHNELLEN不寻常的SCHNITTSTELLEN的FEHLERDETION
公开(公告)号：EP1955163A2
公开(公告)日：2008-08-13
申请号：EP06809185.9
申请日：2006-11-02
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MACRI, Joseph , MOREIN, Stephen , GAUTHIER, Claude , LEE, Ming-Ju, E. , CHEN, Lin
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要指示第二个组件。

9. 发明申请

WO2003014423A1 COMPONENT CATHODE COLLECTOR BAR 审中-公开
标题翻译：组件阴极收集棒
公开(公告)号：WO2003014423A1
公开(公告)日：2003-02-20
申请号：PCT/US2001/024868
申请日：2001-08-09
申请人： ALCOA INC. , GAUTHIER, Claude , FRADET, Claude , PUPUIS, Marc , RICHARD, Daniel
发明人： GAUTHIER, Claude , FRADET, Claude , PUPUIS, Marc , RICHARD, Daniel
IPC分类号： C25C3/16
CPC分类号： C25C3/16 , C25C3/08
摘要： A cathode assembly (2) for use in a Hall-Heroult electrolytic cell, the assembly including a cathode block (4) which receives two primary cathode collector bar (12) and one secondary cathode collector bar (14) disposed therebetween. The primary collector bars (12) each have an electrical interface with the cathode block (4) which is sized to be equal to or greater than an electrical interface between the secondary collector bar (14) and the cathode block (4). The primary collector bars (12) are electrically connected to the cathode block only along an interior portion of the cathode block and the secondary collector bar (14) is fully connected to the cathode block. This arrangement improves current distribution through the cathode assembly by minimizing the amount of current passing through the ends of the cathode block.
摘要翻译：一种用于Hall-Heroult电解池的阴极组件（2），该组件包括一个接纳两个初级阴极集电棒（12）的阴极块（4）和设置在它们之间的一个次级阴极集电棒（14）。主集电棒（12）各自具有与阴极块（4）的电接口，其尺寸设定成等于或大于二次集电棒（14）和阴极块（4）之间的电接口。主集电棒（12）仅沿着阴极块的内部电连接到阴极块，并且次级集电棒（14）完全连接到阴极块。这种布置通过使通过阴极块的端部的电流量最小化来改善通过阴极组件的电流分布。

10. 发明申请

WO2009024882A1 METHOD AND APPARATUS FOR SENDING DATA RELATING TO A TARGET TO A MOBILE DEVICE 审中-公开
标题翻译：将与目标相关的数据发送到移动设备的方法和装置
公开(公告)号：WO2009024882A1
公开(公告)日：2009-02-26
申请号：PCT/IB2008/052829
申请日：2008-07-14
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) , GAUTHIER, Claude , KIROUAC, Martin
发明人： GAUTHIER, Claude , KIROUAC, Martin
IPC分类号： G06F3/01 , G06F3/033
CPC分类号： H04L67/18 , G06F3/014 , G06F3/017 , G06F3/0338 , G06F3/0346 , H04W4/02 , H04W4/21
摘要： The invention relates to a method for sending data relating to a target to a mobile device. Upon moving the mobile device to indicate the target, a vector having an origin at the mobile device and a direction pointing toward the target is computed. The vector is sent to a server for identifying the target. Data relating to the target is sent to the mobile device. The mobile device preferably has a location detecting device, a movements measuring system measuring its movements, a logic module computing the vector and first and second communication modules for exchanging data with the server. The server has first and second communications modules for exchanging data with the mobile device and a logic module for identifying the target using the vector and the location of the target.
摘要翻译：本发明涉及一种用于向移动设备发送与目标有关的数据的方法。在移动移动设备指示目标时，计算在移动设备处具有原点的向量和指向目标的方向。向量发送到服务器以识别目标。与目标相关的数据被发送到移动设备。移动设备优选地具有位置检测设备，测量其移动的移动测量系统，计算向量的逻辑模块以及用于与服务器交换数据的第一和第二通信模块。服务器具有用于与移动设备交换数据的第一和第二通信模块以及用于使用向量和目标位置识别目标的逻辑模块。

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