专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009106788A1 INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE 审中-公开
标题翻译：具有错误维修和故障保修的集成电路
公开(公告)号：WO2009106788A1
公开(公告)日：2009-09-03
申请号：PCT/GB2008/004301
申请日：2008-12-29
申请人： ARM LIMITED , DAS, Shidhartha , BULL, David, Michael , ÖZER, Emre
发明人： DAS, Shidhartha , BULL, David, Michael , ÖZER, Emre
IPC分类号： G01R31/3181 , G06F11/10
CPC分类号： G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
摘要： An integrated circuit (2) is provided with error detection circuitry (10,12) and error repair circuitry (14). Error tolerance circuitry (16) is responsive to a control parameter to selectively disable the error repair circuitry (14). The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behaviour of the circuit or in other ways.
摘要翻译：集成电路（2）具有错误检测电路（10,12）和错误修复电路（14）。误差容限电路（16）响应于控制参数来选择性地禁用误差修复电路（14）。控制参数取决于电路内执行的处理。例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

2. 发明申请

WO2011154719A1 APPARATUS AND METHOD FOR DETECTING AN APPROACHING ERROR CONDITION 审中-公开
标题翻译：用于检测处理错误条件的装置和方法
公开(公告)号：WO2011154719A1
公开(公告)日：2011-12-15
申请号：PCT/GB2011/051022
申请日：2011-05-31
申请人： ARM LIMITED , IDGUNJI, Sachin Satish , DAS, Shidhartha , BULL, David Michael , AITKEN, Robert Campbell
发明人： IDGUNJI, Sachin Satish , DAS, Shidhartha , BULL, David Michael , AITKEN, Robert Campbell
IPC分类号： G06F13/40 , G01R31/317
CPC分类号： G01R31/3016
摘要： An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation. In the first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal, to thereby enable an approaching setup timing error due to a propagation delay within the combinatorial circuitry to be detected. In the second mode of operation, the predetermined timing window is a timing window after the time at which the main storage element latches said value of the output signal such that an approaching hold timing error due to an increase in skew between the first and second clock signals is detected. Such a technique provides a simple and efficient mechanism for detecting a variety of approaching error conditions whilst the second sequence storage structure continues to operate correctly.
摘要翻译：提供了一种用于检测数据处理装置内接近的错误状况的装置和方法。数据处理装置包括第二顺序存储结构，其被配置为根据第二时钟信号锁存由组合电路产生的输出信号。第二顺序存储结构具有主存储元件，用于锁存输出信号的值以提供给后续组合电路;以及转换检测电路，用于检测由主存储元件在预定定时期间锁存的输出信号的值的变化窗口，所述改变指示接近的错误状态，而存储在主存储元件中的值仍然是正确的。第二顺序存储结构可以在第一操作模式或第二操作模式中操作。在第一操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之前的定时窗口，从而使由于组合电路内的传播延迟引起的接近的建立定时误差被检测。在第二操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之后的定时窗口，使得由于第一和第二时钟之间的偏斜增加而接近的保持定时误差检测到信号。这种技术提供了一种用于检测各种接近错误状况的简单有效的机制，同时第二序列存储结构继续正确地操作。

3. 发明申请

WO2006115474A1 ERROR RECOVERY WITHIN PROCESSING STAGES OF AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路的处理阶段出现错误恢复
公开(公告)号：WO2006115474A1
公开(公告)日：2006-11-02
申请号：PCT/US2005/013555
申请日：2005-04-21
申请人： ARM LIMITED , UNIVERSTY OF MICHIGAN , BLAAUW, David, Theodore , BULL, David, Michael , DAS, Shidhartha
发明人： BLAAUW, David, Theodore , BULL, David, Michael , DAS, Shidhartha
IPC分类号： G06F11/14
CPC分类号： G06F11/1407
摘要： An integrated circuit comprises an error detection circuit 3230-1 to 3230-4 operable to detect a transition in the signal value in a predetermined time window, which is indicative of an error in operation of the integrated circuit. The integrated circuit also comprises a storage unit 3296 operable to store a recoverable state of the data processing apparatus comprising at least a subset of architectural state variables corresponding to a programmer's model of the integrated circuit. An error recovery circuit 3250, 3260,3210 is provided as part of the integrated circuit and this serves to enable the integrated circuit to recover from detected errors in operation using the stored recoverable state from the storage unit 3296. An operational parameter controller 3242 of the integrated circuit adjusts the operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature in dependence upon one or more characteristics of detected errors in operation so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括错误检测电路3230-1至3230-4，其可操作以检测指示集成电路的操作中的错误的预定时间窗中的信号值中的转变。集成电路还包括存储单元3296，其可操作以存储数据处理装置的可恢复状态，该可恢复状态包括与集成电路的编程器模型对应的架构状态变量的至少一个子集。作为集成电路的一部分提供了错误恢复电路3250,3260,3210，并且这用于使得集成电路能够使用来自存储单元3296的存储的可恢复状态的操作中的检测到的错误恢复。集成电路根据操作中检测到的错误的一个或多个特性调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度，以保持有限的非零误码率以提高整体性能的方式。

4. 发明申请

WO2007063264A1 DATA PROCESSING SYSTEM 审中-公开
标题翻译：数据处理系统
公开(公告)号：WO2007063264A1
公开(公告)日：2007-06-07
申请号：PCT/GB2005/004636
申请日：2005-12-02
申请人： ARM LIMITED , NEW, David , HOXEY, Paul, Darren , BULL, David, Michael , DAS, Shidhartha
发明人： NEW, David , HOXEY, Paul, Darren , BULL, David, Michael , DAS, Shidhartha
IPC分类号： G11C11/34
CPC分类号： G11C7/08 , G11C7/24 , G11C11/4125 , G11C29/12 , G11C29/12005 , G11C29/26
摘要： A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided (330) for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.
摘要翻译：一种数据处理系统，包括具有多个存储单元（240-246）的存储器阵列和用于读取存储在多个存储器单元之一中的逻辑值的读取电路（310,320）。读取电路（310,320）可操作地执行存储的逻辑值的两个基本上同时的读取。提供电压控制器并且可操作以选择性地改变对存储器阵列的电源电压的电平。提供检测电路（330），用于根据两个基本上同时的读取来检测当电源电压电平导致读取结果不可靠时。

5. 发明申请

WO2017064454A1 AN APPARATUS AND METHOD FOR PROCESSING A RECEIVED INPUT SIGNAL CONTAINING A SEQUENCE OF DATA BLOCKS 审中-公开
标题翻译：用于处理包含数据块序列的接收到的输入信号的装置和方法
公开(公告)号：WO2017064454A1
公开(公告)日：2017-04-20
申请号：PCT/GB2016/052814
申请日：2016-09-12
申请人： ARM LIMITED
发明人： WHATMOUGH, Paul Nicholas , DAS, Shidhartha
IPC分类号： H04L25/06 , H04L25/03 , H04L25/49
CPC分类号： H04L25/069 , H04L25/03318 , H04L25/4902
摘要： An apparatus and method are provided for processing a received input signal comprising a sequence of data blocks. Counter circuitry within the apparatus is arranged to receive a digital representation of the input signal, and for each data block generates a count value indicative of occurrences of a property of the digital representation (for example a rising edge or a falling edge) during an associated data block transmission period. Quantization circuitry then maps each count value to a soft decision value from amongst a predetermined set of soft decision values, where the number of soft decision values in the predetermined set exceeds a number of possible data values of the data block. The output circuitry then generates a digital output signal in dependence on the soft decision values. Such an apparatus has been found to provide a low power technique for a receiver, whilst still enabling the improved sensitivity benefits of using soft decisions to be achieved, and allows the apparatus to be constructed using all digital components.
摘要翻译：提供了一种用于处理包括数据块序列的接收到的输入信号的装置和方法。设备内的计数器电路被设置为接收输入信号的数字表示，并且对于每个数据块，在相关联的过程中产生指示出现数字表示的特性（例如上升沿或下降沿）的计数值数据块传输周期。量化电路然后将每个计数值映射到预定的一组软判决值中的软判定值，其中该预定集合中的软判定值的数量超过数据块的可能数据值的数量。输出电路然后根据软判决值产生数字输出信号。已经发现这种装置为接收机提供低功率技术，同时仍然能够实现使用软判决的改进的灵敏度益处，并且允许使用所有数字组件构建装置。

6. 发明公开

EP3785263A1 METHOD, SYSTEM AND DEVICE FOR INTEGRATION OF VOLATILE AND NON-VOLATILE MEMORY BITCELLS 审中-实审
公开(公告)号：EP3785263A1
公开(公告)日：2021-03-03
申请号：EP19734452.6
申请日：2019-03-22
申请人： ARM Limited
发明人： BHARGAVA, Mudit , DAS, Shidhartha , LATTIMORE, George McNeil , CLINE, Brian Tracy
IPC分类号： G11C11/00 , G11C14/00 , G11C13/00 , G11C7/10 , G11C8/14 , G11C5/02 , G11C5/06 , G11C11/419 , G11C8/08 , G11C7/20

7. 发明公开

EP4139819A1 MODERATOR SYSTEM FOR A SECURITY ANALYTICS FRAMEWORK 审中-实审
公开(公告)号：EP4139819A1
公开(公告)日：2023-03-01
申请号：EP21728961.0
申请日：2021-04-16
申请人： ARM Limited
发明人： YANAMADALA, Subbayya Chowdary , DUBEUF, Jeremy Patrick , VINEYARD, Carl Wayne , BOETTCHER, Matthias Lothar , VINCENT, Hugo John Martin , DAS, Shidhartha
IPC分类号： G06F21/55 , G06N3/02 , G06N20/00

8. 发明公开

EP4139818A1 ANALYTICS PROCESSING CIRCUITRY FOR MITIGATING ATTACKS AGAINST COMPUTING SYSTEMS 审中-实审
公开(公告)号：EP4139818A1
公开(公告)日：2023-03-01
申请号：EP21721588.8
申请日：2021-04-14
申请人： ARM Limited
发明人： YANAMADALA, Subbayya Chowdary , DUBEUF, Jeremy Patrick , VINEYARD, Carl Wayne , BOETTCHER, Matthias Lothar , VINCENT, Hugo John Martin , DAS, Shidhartha
IPC分类号： G06F21/55 , G06F21/56 , G06F21/76

9. 发明申请

WO2021074558A1 ADAPTIVE CODING FOR WIRELESS COMMUNICATION 审中-公开
公开(公告)号：WO2021074558A1
公开(公告)日：2021-04-22
申请号：PCT/GB2020/050713
申请日：2020-03-18
申请人： ARM LIMITED , ECS PARTNERS LIMITED
发明人： GAMAGE, Sahan Sajeewa Hiniduma Udugama , FLETCHER, Benjamin James , DAS, Shidhartha
IPC分类号： H04L1/00 , H04L25/49
摘要： A method and apparatus for transferring data maps the data to a modulation code using an encoder circuit having a configuration. A binary symbol of the data is mapped to a modulation code having a plurality of modulation digits and a modulation signal is generated based on the modulation code. A transmitter drive signal is modulated based on the modulation signal. A configuration of the encoder circuit is set based on a determined performance level. The transmitter drive signal may be used to produce an electromagnetic field by generating a positive, negative or zero electrical current in an induction coil of a first semiconductor die. A current induced by the electromagnetic field in an induction coil of a second semiconductor die is demodulated to recover the data whereby the data is transferred from the first semiconductor die to the second semiconductor die.

10. 发明申请

WO2016174384A1 TRANSITION DETECTION CIRCUITRY AND METHOD OF DETECTING A TRANSITION OF A SIGNAL OCCURRING WITHIN A TIMING WINDOW 审中-公开
标题翻译：过渡检测电路及检测在时序窗口内发生信号转换的方法
公开(公告)号：WO2016174384A1
公开(公告)日：2016-11-03
申请号：PCT/GB2016/050561
申请日：2016-03-03
申请人： ARM LIMITED
发明人： DAS, Shidhartha , BULL, David Michael
IPC分类号： H03K5/1534 , H03K3/037
CPC分类号： H03K5/1534 , H03K3/037 , H03K3/0375
摘要： A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry (30) to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry (35) to control a property of the pulse signal dependent on a timing window indication signal (40). In particular, when the pulse signal is generated at least partly whilst the timing window indication signal is set, the pulse control circuitry (35) controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry (20). In contrast, when the pulse signal is entirely generated whilst the timing window indication signal (40) is cleared, the pulse control circuitry (35) controls the property of the pulse signal such that the generated pulse signal is undetected by the pulse detection circuitry (20). This gives rise to significant area and energy consumption savings, whilst still allowing reliable detection of timing errors.
摘要翻译：提供了一种转换检测电路（20）和这种电路的操作方法，转换检测电路（20）具有接收输入信号（10）的脉冲发生电路（25），并产生响应于输入信号中的转换和脉冲检测电路（30），用于在由脉冲发生电路产生的脉冲信号的检测上断言误差信号。脉冲发生电路具有根据定时窗口指示信号（40）控制脉冲信号的特性的脉冲控制电路（35）。特别地，当在定时窗口指示信号被设定时至少部分产生脉冲信号时，脉冲控制电路（35）控制脉冲信号的特性，使脉冲检测电路（20）检测所产生的脉冲信号，。相反，当脉冲信号在定时窗口指示信号（40）被清除时完全产生时，脉冲控制电路（35）控制脉冲信号的特性，使得产生的脉冲信号不被脉冲检测电路检测（ 20）。这导致显着的面积和能量消耗节省，同时仍然允许可靠地检测定时误差。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式