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1. 发明申请

WO2011154719A1 APPARATUS AND METHOD FOR DETECTING AN APPROACHING ERROR CONDITION 审中-公开
标题翻译：用于检测处理错误条件的装置和方法
公开(公告)号：WO2011154719A1
公开(公告)日：2011-12-15
申请号：PCT/GB2011/051022
申请日：2011-05-31
申请人： ARM LIMITED , IDGUNJI, Sachin Satish , DAS, Shidhartha , BULL, David Michael , AITKEN, Robert Campbell
发明人： IDGUNJI, Sachin Satish , DAS, Shidhartha , BULL, David Michael , AITKEN, Robert Campbell
IPC分类号： G06F13/40 , G01R31/317
CPC分类号： G01R31/3016
摘要： An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation. In the first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal, to thereby enable an approaching setup timing error due to a propagation delay within the combinatorial circuitry to be detected. In the second mode of operation, the predetermined timing window is a timing window after the time at which the main storage element latches said value of the output signal such that an approaching hold timing error due to an increase in skew between the first and second clock signals is detected. Such a technique provides a simple and efficient mechanism for detecting a variety of approaching error conditions whilst the second sequence storage structure continues to operate correctly.
摘要翻译：提供了一种用于检测数据处理装置内接近的错误状况的装置和方法。数据处理装置包括第二顺序存储结构，其被配置为根据第二时钟信号锁存由组合电路产生的输出信号。第二顺序存储结构具有主存储元件，用于锁存输出信号的值以提供给后续组合电路;以及转换检测电路，用于检测由主存储元件在预定定时期间锁存的输出信号的值的变化窗口，所述改变指示接近的错误状态，而存储在主存储元件中的值仍然是正确的。第二顺序存储结构可以在第一操作模式或第二操作模式中操作。在第一操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之前的定时窗口，从而使由于组合电路内的传播延迟引起的接近的建立定时误差被检测。在第二操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之后的定时窗口，使得由于第一和第二时钟之间的偏斜增加而接近的保持定时误差检测到信号。这种技术提供了一种用于检测各种接近错误状况的简单有效的机制，同时第二序列存储结构继续正确地操作。

2. 发明申请

WO2016174384A1 TRANSITION DETECTION CIRCUITRY AND METHOD OF DETECTING A TRANSITION OF A SIGNAL OCCURRING WITHIN A TIMING WINDOW 审中-公开
标题翻译：过渡检测电路及检测在时序窗口内发生信号转换的方法
公开(公告)号：WO2016174384A1
公开(公告)日：2016-11-03
申请号：PCT/GB2016/050561
申请日：2016-03-03
申请人： ARM LIMITED
发明人： DAS, Shidhartha , BULL, David Michael
IPC分类号： H03K5/1534 , H03K3/037
CPC分类号： H03K5/1534 , H03K3/037 , H03K3/0375
摘要： A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry (30) to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry (35) to control a property of the pulse signal dependent on a timing window indication signal (40). In particular, when the pulse signal is generated at least partly whilst the timing window indication signal is set, the pulse control circuitry (35) controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry (20). In contrast, when the pulse signal is entirely generated whilst the timing window indication signal (40) is cleared, the pulse control circuitry (35) controls the property of the pulse signal such that the generated pulse signal is undetected by the pulse detection circuitry (20). This gives rise to significant area and energy consumption savings, whilst still allowing reliable detection of timing errors.
摘要翻译：提供了一种转换检测电路（20）和这种电路的操作方法，转换检测电路（20）具有接收输入信号（10）的脉冲发生电路（25），并产生响应于输入信号中的转换和脉冲检测电路（30），用于在由脉冲发生电路产生的脉冲信号的检测上断言误差信号。脉冲发生电路具有根据定时窗口指示信号（40）控制脉冲信号的特性的脉冲控制电路（35）。特别地，当在定时窗口指示信号被设定时至少部分产生脉冲信号时，脉冲控制电路（35）控制脉冲信号的特性，使脉冲检测电路（20）检测所产生的脉冲信号，。相反，当脉冲信号在定时窗口指示信号（40）被清除时完全产生时，脉冲控制电路（35）控制脉冲信号的特性，使得产生的脉冲信号不被脉冲检测电路检测（ 20）。这导致显着的面积和能量消耗节省，同时仍然允许可靠地检测定时误差。

3. 发明申请

WO2015170072A1 CLOCK FREQUENCY REDUCTION FOR AN ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备的时钟频率降低
公开(公告)号：WO2015170072A1
公开(公告)日：2015-11-12
申请号：PCT/GB2015/050736
申请日：2015-03-13
申请人： ARM LIMITED
发明人： WHATMOUGH, Paul Nicholas , BULL, David Michael , DAS, Shidhartha
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F1/08
摘要： An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.
摘要翻译：电子设备（20）具有用于在时钟路径上传播时钟信号和时钟传播元件（26）的时钟路径（24）。耦合到时钟路径（24）的模拟元件（30）根据第一信号（32）的模拟电平而变化用于时钟传播元件（26）触发时钟信号转换的切换延迟。第一个信号是数字采样信号。这提供了即使第一信号是亚稳态信号来提供时钟频率的快速降低的机制，其可用于避免由电压降引起的错误。

4. 发明申请

WO2016193657A1 COMMUNICATIONS DEVICE AND METHOD 审中-公开
标题翻译：通信设备和方法
公开(公告)号：WO2016193657A1
公开(公告)日：2016-12-08
申请号：PCT/GB2016/051056
申请日：2016-04-15
申请人： ARM LIMITED
发明人： WHATMOUGH, Paul Nicholas , SMART, George , DAS, Shidhartha , BULL, David Michael
IPC分类号： H04B1/3827 , H04B13/00
CPC分类号： H04B13/005 , H04B1/385
摘要： A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.
摘要翻译：设备包括被配置为将信号耦合到通信路径和从包括人或动物主体的至少一部分的通信路径耦合的耦合; 耦合到所述耦合并被配置为经由所述通信路径不时地传送至少预定时间持续时间的数据信号的数据发射器; 以及数据接收器，其耦合到所述耦合并且被配置为在由所述数据发射器连续传输所述数据信号之间的一个或多个连续检测实例的集合处检测所述通信路径上的信号的存在，所述数据接收器被配置为使得一组的连续检测实例在时间上分开不超过预定的时间持续时间; 所述设备被配置为响应于数据接收器对通信路径上的信号的存在的检测而发起处理操作。

5. 发明申请

WO2010007367A1 ERROR MANAGEMENT 审中-公开
标题翻译：错误管理
公开(公告)号：WO2010007367A1
公开(公告)日：2010-01-21
申请号：PCT/GB2009/001751
申请日：2009-07-15
申请人： ARM Limited , KERSHAW, Daniel , BULL, David Michael , WILDER, Mladen
发明人： KERSHAW, Daniel , BULL, David Michael , WILDER, Mladen
IPC分类号： H04L1/20 , H04L1/00 , G06F1/32 , H04B7/06
CPC分类号： H04L1/20 , H04B7/0619 , H04B7/0689 , H04B7/0691 , H04B17/336 , H04L1/0002 , H04L1/0025 , H04L25/0202
摘要： An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device. The digital performance data provides the control circuitry with additional information for use in identifying where errors in signal processing are arising, enabling an informed decision be made to modify the operation of either the transmitting device or receiving device in some way, either to reduce the occurrence of errors in the output signal or to improve the speed and/or efficiency of the transmitter and/or receiver.
摘要翻译：描述了经由通信信道从发送设备接收数据的电子设备。电子设备包括数字处理电路，其被布置成处理经由通信信道接收的数据以产生输出数据，布置成检测输出数据中的错误的错误检测电路以及被设置为监视由数字处理进行的数字处理的质量的监视电路电路并产生指示数字处理的监控质量的数字性能数据。电子设备还包括响应于错误信息的控制电路，错误信息包括由错误检测电路检测到的错误和由监控电路产生的性能数据，以修改发送设备和电子设备中的一个或两者的操作。数字性能数据为控制电路提供附加信息，用于识别信号处理中的错误出现位置，使得能够以某种方式做出明智的决定以修改发射设备或接收设备的操作，以减少发生的输出信号中的错误或提高发射机和/或接收机的速度和/或效率。

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